thread_context.hh (9426:0548b3e9734d) | thread_context.hh (9920:028e4da64b42) |
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1/* 2 * Copyright (c) 2011-2012 ARM Limited | 1/* 2 * Copyright (c) 2011-2012 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. |
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3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 200 unchanged lines hidden (view full) --- 211 { return actualTC->readIntReg(reg_idx); } 212 213 FloatReg readFloatReg(int reg_idx) 214 { return actualTC->readFloatReg(reg_idx); } 215 216 FloatRegBits readFloatRegBits(int reg_idx) 217 { return actualTC->readFloatRegBits(reg_idx); } 218 | 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 200 unchanged lines hidden (view full) --- 212 { return actualTC->readIntReg(reg_idx); } 213 214 FloatReg readFloatReg(int reg_idx) 215 { return actualTC->readFloatReg(reg_idx); } 216 217 FloatRegBits readFloatRegBits(int reg_idx) 218 { return actualTC->readFloatRegBits(reg_idx); } 219 |
220 CCReg readCCReg(int reg_idx) 221 { return actualTC->readCCReg(reg_idx); } 222 |
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219 void setIntReg(int reg_idx, uint64_t val) 220 { 221 actualTC->setIntReg(reg_idx, val); 222 checkerTC->setIntReg(reg_idx, val); 223 } 224 225 void setFloatReg(int reg_idx, FloatReg val) 226 { 227 actualTC->setFloatReg(reg_idx, val); 228 checkerTC->setFloatReg(reg_idx, val); 229 } 230 231 void setFloatRegBits(int reg_idx, FloatRegBits val) 232 { 233 actualTC->setFloatRegBits(reg_idx, val); 234 checkerTC->setFloatRegBits(reg_idx, val); 235 } 236 | 223 void setIntReg(int reg_idx, uint64_t val) 224 { 225 actualTC->setIntReg(reg_idx, val); 226 checkerTC->setIntReg(reg_idx, val); 227 } 228 229 void setFloatReg(int reg_idx, FloatReg val) 230 { 231 actualTC->setFloatReg(reg_idx, val); 232 checkerTC->setFloatReg(reg_idx, val); 233 } 234 235 void setFloatRegBits(int reg_idx, FloatRegBits val) 236 { 237 actualTC->setFloatRegBits(reg_idx, val); 238 checkerTC->setFloatRegBits(reg_idx, val); 239 } 240 |
241 void setCCReg(int reg_idx, CCReg val) 242 { 243 actualTC->setCCReg(reg_idx, val); 244 checkerTC->setCCReg(reg_idx, val); 245 } 246 |
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237 /** Reads this thread's PC state. */ 238 TheISA::PCState pcState() 239 { return actualTC->pcState(); } 240 241 /** Sets this thread's PC state. */ 242 void pcState(const TheISA::PCState &val) 243 { 244 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", --- 39 unchanged lines hidden (view full) --- 284 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 285 " and O3..\n", misc_reg); 286 checkerTC->setMiscReg(misc_reg, val); 287 actualTC->setMiscReg(misc_reg, val); 288 } 289 290 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 291 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } | 247 /** Reads this thread's PC state. */ 248 TheISA::PCState pcState() 249 { return actualTC->pcState(); } 250 251 /** Sets this thread's PC state. */ 252 void pcState(const TheISA::PCState &val) 253 { 254 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", --- 39 unchanged lines hidden (view full) --- 294 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 295 " and O3..\n", misc_reg); 296 checkerTC->setMiscReg(misc_reg, val); 297 actualTC->setMiscReg(misc_reg, val); 298 } 299 300 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 301 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } |
302 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } |
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292 293 unsigned readStCondFailures() 294 { return actualTC->readStCondFailures(); } 295 296 void setStCondFailures(unsigned sc_failures) 297 { 298 actualTC->setStCondFailures(sc_failures); 299 } --- 15 unchanged lines hidden (view full) --- 315 void setFloatRegFlat(int idx, FloatReg val) 316 { actualTC->setFloatRegFlat(idx, val); } 317 318 FloatRegBits readFloatRegBitsFlat(int idx) 319 { return actualTC->readFloatRegBitsFlat(idx); } 320 321 void setFloatRegBitsFlat(int idx, FloatRegBits val) 322 { actualTC->setFloatRegBitsFlat(idx, val); } | 303 304 unsigned readStCondFailures() 305 { return actualTC->readStCondFailures(); } 306 307 void setStCondFailures(unsigned sc_failures) 308 { 309 actualTC->setStCondFailures(sc_failures); 310 } --- 15 unchanged lines hidden (view full) --- 326 void setFloatRegFlat(int idx, FloatReg val) 327 { actualTC->setFloatRegFlat(idx, val); } 328 329 FloatRegBits readFloatRegBitsFlat(int idx) 330 { return actualTC->readFloatRegBitsFlat(idx); } 331 332 void setFloatRegBitsFlat(int idx, FloatRegBits val) 333 { actualTC->setFloatRegBitsFlat(idx, val); } |
334 335 CCReg readCCRegFlat(int idx) 336 { return actualTC->readCCRegFlat(idx); } 337 338 void setCCRegFlat(int idx, CCReg val) 339 { actualTC->setCCRegFlat(idx, val); } |
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323}; 324 325#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ | 340}; 341 342#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |