thread_context.hh (8733:64a7bf8fa56c) | thread_context.hh (8754:0996451df6de) |
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1/* | 1/* |
2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * | |
14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 43#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 44#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 45 46#include "arch/types.hh" 47#include "config/the_isa.hh" 48#include "cpu/checker/cpu.hh" 49#include "cpu/simple_thread.hh" 50#include "cpu/thread_context.hh" | 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 32#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 33 34#include "arch/types.hh" 35#include "config/the_isa.hh" 36#include "cpu/checker/cpu.hh" 37#include "cpu/simple_thread.hh" 38#include "cpu/thread_context.hh" |
51#include "debug/Checker.hh" | |
52 53class EndQuiesceEvent; 54namespace TheISA { 55 namespace Kernel { 56 class Statistics; 57 }; 58}; 59 --- 25 unchanged lines hidden (view full) --- 85 SimpleThread *checkerTC; 86 /** Pointer to the checker CPU. */ 87 CheckerCPU *checkerCPU; 88 89 public: 90 91 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 92 | 39 40class EndQuiesceEvent; 41namespace TheISA { 42 namespace Kernel { 43 class Statistics; 44 }; 45}; 46 --- 25 unchanged lines hidden (view full) --- 72 SimpleThread *checkerTC; 73 /** Pointer to the checker CPU. */ 74 CheckerCPU *checkerCPU; 75 76 public: 77 78 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 79 |
93 int cpuId() { return actualTC->cpuId(); } 94 95 int contextId() { return actualTC->contextId(); } 96 97 void setContextId(int id) | 80 void setCpuId(int id) |
98 { | 81 { |
99 actualTC->setContextId(id); 100 checkerTC->setContextId(id); | 82 actualTC->setCpuId(id); 83 checkerTC->setCpuId(id); |
101 } 102 | 84 } 85 |
103 /** Returns this thread's ID number. */ 104 int threadId() { return actualTC->threadId(); } 105 void setThreadId(int id) 106 { 107 checkerTC->setThreadId(id); 108 actualTC->setThreadId(id); 109 } | 86 int cpuId() { return actualTC->cpuId(); } |
110 111 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 112 113 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 114 | 87 88 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 89 90 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 91 |
115 BaseCPU *getCheckerCpuPtr() { return checkerTC->getCpuPtr(); } 116 117 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 118 | 92#if FULL_SYSTEM |
119 System *getSystemPtr() { return actualTC->getSystemPtr(); } 120 | 93 System *getSystemPtr() { return actualTC->getSystemPtr(); } 94 |
121#if FULL_SYSTEM | |
122 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 123 124 TheISA::Kernel::Statistics *getKernelStats() 125 { return actualTC->getKernelStats(); } 126 | 95 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 96 97 TheISA::Kernel::Statistics *getKernelStats() 98 { return actualTC->getKernelStats(); } 99 |
127 PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 128 129 FSTranslatingPortProxy* getVirtProxy() 130 { return actualTC->getVirtProxy(); } 131 132 //XXX: How does this work now? 133 void initMemProxies(ThreadContext *tc) 134 { actualTC->initMemProxies(tc); } 135 136 void connectMemPorts(ThreadContext *tc) 137 { 138 actualTC->connectMemPorts(tc); 139 } | 100 VirtualPort *getVirtPort() 101 { return actualTC->getVirtPort(); } |
140#else | 102#else |
141 SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } | 103 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } |
142 143 Process *getProcessPtr() { return actualTC->getProcessPtr(); } | 104 105 Process *getProcessPtr() { return actualTC->getProcessPtr(); } |
144 145 /** Executes a syscall in SE mode. */ 146 void syscall(int64_t callnum) 147 { return actualTC->syscall(callnum); } | |
148#endif 149 | 106#endif 107 |
108 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 109 |
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150 Status status() const { return actualTC->status(); } 151 152 void setStatus(Status new_status) 153 { 154 actualTC->setStatus(new_status); 155 checkerTC->setStatus(new_status); 156 } 157 158 /// Set the status to Active. Optional delay indicates number of 159 /// cycles to wait before beginning execution. 160 void activate(int delay = 1) { actualTC->activate(delay); } 161 162 /// Set the status to Suspended. | 110 Status status() const { return actualTC->status(); } 111 112 void setStatus(Status new_status) 113 { 114 actualTC->setStatus(new_status); 115 checkerTC->setStatus(new_status); 116 } 117 118 /// Set the status to Active. Optional delay indicates number of 119 /// cycles to wait before beginning execution. 120 void activate(int delay = 1) { actualTC->activate(delay); } 121 122 /// Set the status to Suspended. |
163 void suspend(int delay) { actualTC->suspend(delay); } | 123 void suspend() { actualTC->suspend(); } |
164 165 /// Set the status to Halted. | 124 125 /// Set the status to Halted. |
166 void halt(int delay) { actualTC->halt(delay); } | 126 void halt() { actualTC->halt(); } |
167 168#if FULL_SYSTEM 169 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 170#endif 171 172 void takeOverFrom(ThreadContext *oldContext) 173 { 174 actualTC->takeOverFrom(oldContext); 175 checkerTC->copyState(oldContext); 176 } 177 | 127 128#if FULL_SYSTEM 129 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 130#endif 131 132 void takeOverFrom(ThreadContext *oldContext) 133 { 134 actualTC->takeOverFrom(oldContext); 135 checkerTC->copyState(oldContext); 136 } 137 |
178 void regStats(const std::string &name) 179 { 180 actualTC->regStats(name); 181 checkerTC->regStats(name); 182 } | 138 void regStats(const std::string &name) { actualTC->regStats(name); } |
183 184 void serialize(std::ostream &os) { actualTC->serialize(os); } 185 void unserialize(Checkpoint *cp, const std::string §ion) 186 { actualTC->unserialize(cp, section); } 187 188#if FULL_SYSTEM 189 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 190 191 Tick readLastActivate() { return actualTC->readLastActivate(); } 192 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 193 194 void profileClear() { return actualTC->profileClear(); } 195 void profileSample() { return actualTC->profileSample(); } 196#endif 197 | 139 140 void serialize(std::ostream &os) { actualTC->serialize(os); } 141 void unserialize(Checkpoint *cp, const std::string §ion) 142 { actualTC->unserialize(cp, section); } 143 144#if FULL_SYSTEM 145 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 146 147 Tick readLastActivate() { return actualTC->readLastActivate(); } 148 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 149 150 void profileClear() { return actualTC->profileClear(); } 151 void profileSample() { return actualTC->profileSample(); } 152#endif 153 |
154 int threadId() { return actualTC->threadId(); } 155 |
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198 // @todo: Do I need this? 199 void copyArchRegs(ThreadContext *tc) 200 { 201 actualTC->copyArchRegs(tc); 202 checkerTC->copyArchRegs(tc); 203 } 204 205 void clearArchRegs() --- 27 unchanged lines hidden (view full) --- 233 } 234 235 void setFloatRegBits(int reg_idx, FloatRegBits val) 236 { 237 actualTC->setFloatRegBits(reg_idx, val); 238 checkerTC->setFloatRegBits(reg_idx, val); 239 } 240 | 156 // @todo: Do I need this? 157 void copyArchRegs(ThreadContext *tc) 158 { 159 actualTC->copyArchRegs(tc); 160 checkerTC->copyArchRegs(tc); 161 } 162 163 void clearArchRegs() --- 27 unchanged lines hidden (view full) --- 191 } 192 193 void setFloatRegBits(int reg_idx, FloatRegBits val) 194 { 195 actualTC->setFloatRegBits(reg_idx, val); 196 checkerTC->setFloatRegBits(reg_idx, val); 197 } 198 |
241 /** Reads this thread's PC state. */ 242 TheISA::PCState pcState() 243 { return actualTC->pcState(); } | 199 uint64_t readPC() { return actualTC->readPC(); } |
244 | 200 |
245 /** Sets this thread's PC state. */ 246 void pcState(const TheISA::PCState &val) | 201 void setPC(uint64_t val) |
247 { | 202 { |
248 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 249 val, checkerTC->pcState()); 250 checkerTC->pcState(val); | 203 actualTC->setPC(val); 204 checkerTC->setPC(val); |
251 checkerCPU->recordPCChange(val); | 205 checkerCPU->recordPCChange(val); |
252 return actualTC->pcState(val); | |
253 } 254 | 206 } 207 |
255 void pcStateNoRecord(const TheISA::PCState &val) | 208 uint64_t readNextPC() { return actualTC->readNextPC(); } 209 210 void setNextPC(uint64_t val) |
256 { | 211 { |
257 return actualTC->pcState(val); | 212 actualTC->setNextPC(val); 213 checkerTC->setNextPC(val); 214 checkerCPU->recordNextPCChange(val); |
258 } 259 | 215 } 216 |
260 /** Reads this thread's PC. */ 261 Addr instAddr() 262 { return actualTC->instAddr(); } | 217 uint64_t readNextNPC() { return actualTC->readNextNPC(); } |
263 | 218 |
264 /** Reads this thread's next PC. */ 265 Addr nextInstAddr() 266 { return actualTC->nextInstAddr(); } | 219 void setNextNPC(uint64_t val) 220 { 221 actualTC->setNextNPC(val); 222 checkerTC->setNextNPC(val); 223 checkerCPU->recordNextPCChange(val); 224 } |
267 | 225 |
268 /** Reads this thread's next PC. */ 269 MicroPC microPC() 270 { return actualTC->microPC(); } 271 | |
272 MiscReg readMiscRegNoEffect(int misc_reg) 273 { return actualTC->readMiscRegNoEffect(misc_reg); } 274 275 MiscReg readMiscReg(int misc_reg) 276 { return actualTC->readMiscReg(misc_reg); } 277 278 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 279 { | 226 MiscReg readMiscRegNoEffect(int misc_reg) 227 { return actualTC->readMiscRegNoEffect(misc_reg); } 228 229 MiscReg readMiscReg(int misc_reg) 230 { return actualTC->readMiscReg(misc_reg); } 231 232 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 233 { |
280 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 281 " and O3..\n", misc_reg); | |
282 checkerTC->setMiscRegNoEffect(misc_reg, val); 283 actualTC->setMiscRegNoEffect(misc_reg, val); 284 } 285 286 void setMiscReg(int misc_reg, const MiscReg &val) 287 { | 234 checkerTC->setMiscRegNoEffect(misc_reg, val); 235 actualTC->setMiscRegNoEffect(misc_reg, val); 236 } 237 238 void setMiscReg(int misc_reg, const MiscReg &val) 239 { |
288 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 289 " and O3..\n", misc_reg); | |
290 checkerTC->setMiscReg(misc_reg, val); 291 actualTC->setMiscReg(misc_reg, val); 292 } 293 | 240 checkerTC->setMiscReg(misc_reg, val); 241 actualTC->setMiscReg(misc_reg, val); 242 } 243 |
294 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 295 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 296 | |
297 unsigned readStCondFailures() 298 { return actualTC->readStCondFailures(); } 299 300 void setStCondFailures(unsigned sc_failures) 301 { | 244 unsigned readStCondFailures() 245 { return actualTC->readStCondFailures(); } 246 247 void setStCondFailures(unsigned sc_failures) 248 { |
249 checkerTC->setStCondFailures(sc_failures); |
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302 actualTC->setStCondFailures(sc_failures); 303 } 304 305 // @todo: Fix this! 306 bool misspeculating() { return actualTC->misspeculating(); } 307 308#if !FULL_SYSTEM 309 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 310#endif 311}; 312 313#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ | 250 actualTC->setStCondFailures(sc_failures); 251 } 252 253 // @todo: Fix this! 254 bool misspeculating() { return actualTC->misspeculating(); } 255 256#if !FULL_SYSTEM 257 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 258#endif 259}; 260 261#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |