thread_context.hh (3225:9872d6c27222) thread_context.hh (3468:cf23ad1ceef2)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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82
83 int readCpuId() { return actualTC->readCpuId(); }
84
85#if FULL_SYSTEM
86 System *getSystemPtr() { return actualTC->getSystemPtr(); }
87
88 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
89
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 73 unchanged lines hidden (view full) ---

82
83 int readCpuId() { return actualTC->readCpuId(); }
84
85#if FULL_SYSTEM
86 System *getSystemPtr() { return actualTC->getSystemPtr(); }
87
88 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
89
90 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
90 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
91
91
92 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
92 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
93
94 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
95
96 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
97
98 VirtualPort *getVirtPort(ThreadContext *tc = NULL)
99 { return actualTC->getVirtPort(); }
100

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243 actualTC->setNextNPC(val);
244 checkerTC->setNextNPC(val);
245 checkerCPU->recordNextPCChange(val);
246 }
247
248 MiscReg readMiscReg(int misc_reg)
249 { return actualTC->readMiscReg(misc_reg); }
250
93
94 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
95
96 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
97
98 VirtualPort *getVirtPort(ThreadContext *tc = NULL)
99 { return actualTC->getVirtPort(); }
100

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243 actualTC->setNextNPC(val);
244 checkerTC->setNextNPC(val);
245 checkerCPU->recordNextPCChange(val);
246 }
247
248 MiscReg readMiscReg(int misc_reg)
249 { return actualTC->readMiscReg(misc_reg); }
250
251 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
252 { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
251 MiscReg readMiscRegWithEffect(int misc_reg)
252 { return actualTC->readMiscRegWithEffect(misc_reg); }
253
253
254 Fault setMiscReg(int misc_reg, const MiscReg &val)
254 void setMiscReg(int misc_reg, const MiscReg &val)
255 {
256 checkerTC->setMiscReg(misc_reg, val);
255 {
256 checkerTC->setMiscReg(misc_reg, val);
257 return actualTC->setMiscReg(misc_reg, val);
257 actualTC->setMiscReg(misc_reg, val);
258 }
259
258 }
259
260 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
260 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
261 {
262 checkerTC->setMiscRegWithEffect(misc_reg, val);
261 {
262 checkerTC->setMiscRegWithEffect(misc_reg, val);
263 return actualTC->setMiscRegWithEffect(misc_reg, val);
263 actualTC->setMiscRegWithEffect(misc_reg, val);
264 }
265
266 unsigned readStCondFailures()
267 { return actualTC->readStCondFailures(); }
268
269 void setStCondFailures(unsigned sc_failures)
270 {
271 checkerTC->setStCondFailures(sc_failures);

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265
266 unsigned readStCondFailures()
267 { return actualTC->readStCondFailures(); }
268
269 void setStCondFailures(unsigned sc_failures)
270 {
271 checkerTC->setStCondFailures(sc_failures);

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