thread_context.hh (13693:85fa3a41014b) thread_context.hh (13865:cca49fc49c57)
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 84 unchanged lines hidden (view full) ---

93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const override { return actualTC->socketId(); }
96
97 int cpuId() const override { return actualTC->cpuId(); }
98
99 ContextID contextId() const override { return actualTC->contextId(); }
100
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 84 unchanged lines hidden (view full) ---

93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const override { return actualTC->socketId(); }
96
97 int cpuId() const override { return actualTC->cpuId(); }
98
99 ContextID contextId() const override { return actualTC->contextId(); }
100
101 void setContextId(ContextID id)override
101 void
102 setContextId(ContextID id) override
102 {
103 actualTC->setContextId(id);
104 checkerTC->setContextId(id);
105 }
106
107 /** Returns this thread's ID number. */
108 int threadId() const override { return actualTC->threadId(); }
103 {
104 actualTC->setContextId(id);
105 checkerTC->setContextId(id);
106 }
107
108 /** Returns this thread's ID number. */
109 int threadId() const override { return actualTC->threadId(); }
109 void setThreadId(int id) override
110 void
111 setThreadId(int id) override
110 {
111 checkerTC->setThreadId(id);
112 actualTC->setThreadId(id);
113 }
114
115 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
116
117 BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
118
112 {
113 checkerTC->setThreadId(id);
114 actualTC->setThreadId(id);
115 }
116
117 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
118
119 BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
120
119 CheckerCPU *getCheckerCpuPtr()override
121 CheckerCPU *
122 getCheckerCpuPtr() override
120 {
121 return checkerCPU;
122 }
123
124 TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
125
123 {
124 return checkerCPU;
125 }
126
127 TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
128
126 TheISA::Decoder *getDecoderPtr() override {
129 TheISA::Decoder *
130 getDecoderPtr() override
131 {
127 return actualTC->getDecoderPtr();
128 }
129
130 System *getSystemPtr() override { return actualTC->getSystemPtr(); }
131
132 return actualTC->getDecoderPtr();
133 }
134
135 System *getSystemPtr() override { return actualTC->getSystemPtr(); }
136
132 TheISA::Kernel::Statistics *getKernelStats()override
133 { return actualTC->getKernelStats(); }
137 TheISA::Kernel::Statistics *
138 getKernelStats() override
139 {
140 return actualTC->getKernelStats();
141 }
134
135 Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
136
137 void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
138
139 PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
140
142
143 Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
144
145 void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
146
147 PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
148
141 FSTranslatingPortProxy &getVirtProxy() override
142 { return actualTC->getVirtProxy(); }
149 FSTranslatingPortProxy &
150 getVirtProxy() override
151 {
152 return actualTC->getVirtProxy();
153 }
143
154
144 void initMemProxies(ThreadContext *tc) override
145 { actualTC->initMemProxies(tc); }
155 void
156 initMemProxies(ThreadContext *tc) override
157 {
158 actualTC->initMemProxies(tc);
159 }
146
160
147 void connectMemPorts(ThreadContext *tc)
161 void
162 connectMemPorts(ThreadContext *tc)
148 {
149 actualTC->connectMemPorts(tc);
150 }
151
163 {
164 actualTC->connectMemPorts(tc);
165 }
166
152 SETranslatingPortProxy &getMemProxy() override {
167 SETranslatingPortProxy &
168 getMemProxy() override
169 {
153 return actualTC->getMemProxy();
154 }
155
156 /** Executes a syscall in SE mode. */
170 return actualTC->getMemProxy();
171 }
172
173 /** Executes a syscall in SE mode. */
157 void syscall(int64_t callnum, Fault *fault)override
158 { return actualTC->syscall(callnum, fault); }
174 void
175 syscall(int64_t callnum, Fault *fault) override
176 {
177 return actualTC->syscall(callnum, fault);
178 }
159
160 Status status() const override { return actualTC->status(); }
161
179
180 Status status() const override { return actualTC->status(); }
181
162 void setStatus(Status new_status) override
182 void
183 setStatus(Status new_status) override
163 {
164 actualTC->setStatus(new_status);
165 checkerTC->setStatus(new_status);
166 }
167
168 /// Set the status to Active.
169 void activate() override { actualTC->activate(); }
170
171 /// Set the status to Suspended.
184 {
185 actualTC->setStatus(new_status);
186 checkerTC->setStatus(new_status);
187 }
188
189 /// Set the status to Active.
190 void activate() override { actualTC->activate(); }
191
192 /// Set the status to Suspended.
172 void suspend() override{ actualTC->suspend(); }
193 void suspend() override { actualTC->suspend(); }
173
174 /// Set the status to Halted.
194
195 /// Set the status to Halted.
175 void halt() override{ actualTC->halt(); }
196 void halt() override { actualTC->halt(); }
176
197
177 void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); }
198 void dumpFuncProfile() override { actualTC->dumpFuncProfile(); }
178
199
179 void takeOverFrom(ThreadContext *oldContext) override
200 void
201 takeOverFrom(ThreadContext *oldContext) override
180 {
181 actualTC->takeOverFrom(oldContext);
182 checkerTC->copyState(oldContext);
183 }
184
202 {
203 actualTC->takeOverFrom(oldContext);
204 checkerTC->copyState(oldContext);
205 }
206
185 void regStats(const std::string &name) override
207 void
208 regStats(const std::string &name) override
186 {
187 actualTC->regStats(name);
188 checkerTC->regStats(name);
189 }
190
209 {
210 actualTC->regStats(name);
211 checkerTC->regStats(name);
212 }
213
191 EndQuiesceEvent *getQuiesceEvent() override {
214 EndQuiesceEvent *
215 getQuiesceEvent() override
216 {
192 return actualTC->getQuiesceEvent();
193 }
194
217 return actualTC->getQuiesceEvent();
218 }
219
195 Tick readLastActivate() override{ return actualTC->readLastActivate(); }
196 Tick readLastSuspend() override{ return actualTC->readLastSuspend(); }
220 Tick readLastActivate() override { return actualTC->readLastActivate(); }
221 Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
197
222
198 void profileClear() override{ return actualTC->profileClear(); }
199 void profileSample() override{ return actualTC->profileSample(); }
223 void profileClear() override { return actualTC->profileClear(); }
224 void profileSample() override { return actualTC->profileSample(); }
200
201 // @todo: Do I need this?
225
226 // @todo: Do I need this?
202 void copyArchRegs(ThreadContext *tc) override
227 void
228 copyArchRegs(ThreadContext *tc) override
203 {
204 actualTC->copyArchRegs(tc);
205 checkerTC->copyArchRegs(tc);
206 }
207
229 {
230 actualTC->copyArchRegs(tc);
231 checkerTC->copyArchRegs(tc);
232 }
233
208 void clearArchRegs() override
234 void
235 clearArchRegs() override
209 {
210 actualTC->clearArchRegs();
211 checkerTC->clearArchRegs();
212 }
213
214 //
215 // New accessors for new decoder.
216 //
236 {
237 actualTC->clearArchRegs();
238 checkerTC->clearArchRegs();
239 }
240
241 //
242 // New accessors for new decoder.
243 //
217 RegVal readIntReg(int reg_idx) override {
244 RegVal
245 readIntReg(RegIndex reg_idx) const override
246 {
218 return actualTC->readIntReg(reg_idx);
219 }
220
221 RegVal
247 return actualTC->readIntReg(reg_idx);
248 }
249
250 RegVal
222 readFloatReg(int reg_idx) override
251 readFloatReg(RegIndex reg_idx) const override
223 {
224 return actualTC->readFloatReg(reg_idx);
225 }
226
252 {
253 return actualTC->readFloatReg(reg_idx);
254 }
255
227 const VecRegContainer& readVecReg (const RegId& reg) const override
228 { return actualTC->readVecReg(reg); }
256 const VecRegContainer &
257 readVecReg (const RegId &reg) const override
258 {
259 return actualTC->readVecReg(reg);
260 }
229
230 /**
231 * Read vector register for modification, hierarchical indexing.
232 */
261
262 /**
263 * Read vector register for modification, hierarchical indexing.
264 */
233 VecRegContainer& getWritableVecReg (const RegId& reg) override
234 { return actualTC->getWritableVecReg(reg); }
265 VecRegContainer &
266 getWritableVecReg (const RegId &reg) override
267 {
268 return actualTC->getWritableVecReg(reg);
269 }
235
236 /** Vector Register Lane Interfaces. */
237 /** @{ */
238 /** Reads source vector 8bit operand. */
239 ConstVecLane8
270
271 /** Vector Register Lane Interfaces. */
272 /** @{ */
273 /** Reads source vector 8bit operand. */
274 ConstVecLane8
240 readVec8BitLaneReg(const RegId& reg) const override
241 { return actualTC->readVec8BitLaneReg(reg); }
275 readVec8BitLaneReg(const RegId &reg) const override
276 {
277 return actualTC->readVec8BitLaneReg(reg);
278 }
242
243 /** Reads source vector 16bit operand. */
244 ConstVecLane16
279
280 /** Reads source vector 16bit operand. */
281 ConstVecLane16
245 readVec16BitLaneReg(const RegId& reg) const override
246 { return actualTC->readVec16BitLaneReg(reg); }
282 readVec16BitLaneReg(const RegId &reg) const override
283 {
284 return actualTC->readVec16BitLaneReg(reg);
285 }
247
248 /** Reads source vector 32bit operand. */
249 ConstVecLane32
286
287 /** Reads source vector 32bit operand. */
288 ConstVecLane32
250 readVec32BitLaneReg(const RegId& reg) const override
251 { return actualTC->readVec32BitLaneReg(reg); }
289 readVec32BitLaneReg(const RegId &reg) const override
290 {
291 return actualTC->readVec32BitLaneReg(reg);
292 }
252
253 /** Reads source vector 64bit operand. */
254 ConstVecLane64
293
294 /** Reads source vector 64bit operand. */
295 ConstVecLane64
255 readVec64BitLaneReg(const RegId& reg) const override
256 { return actualTC->readVec64BitLaneReg(reg); }
296 readVec64BitLaneReg(const RegId &reg) const override
297 {
298 return actualTC->readVec64BitLaneReg(reg);
299 }
257
258 /** Write a lane of the destination vector register. */
300
301 /** Write a lane of the destination vector register. */
259 virtual void setVecLane(const RegId& reg,
260 const LaneData<LaneSize::Byte>& val) override
261 { return actualTC->setVecLane(reg, val); }
262 virtual void setVecLane(const RegId& reg,
263 const LaneData<LaneSize::TwoByte>& val) override
264 { return actualTC->setVecLane(reg, val); }
265 virtual void setVecLane(const RegId& reg,
266 const LaneData<LaneSize::FourByte>& val) override
267 { return actualTC->setVecLane(reg, val); }
268 virtual void setVecLane(const RegId& reg,
269 const LaneData<LaneSize::EightByte>& val) override
270 { return actualTC->setVecLane(reg, val); }
302 virtual void
303 setVecLane(const RegId &reg,
304 const LaneData<LaneSize::Byte> &val) override
305 {
306 return actualTC->setVecLane(reg, val);
307 }
308 virtual void
309 setVecLane(const RegId &reg,
310 const LaneData<LaneSize::TwoByte> &val) override
311 {
312 return actualTC->setVecLane(reg, val);
313 }
314 virtual void
315 setVecLane(const RegId &reg,
316 const LaneData<LaneSize::FourByte> &val) override
317 {
318 return actualTC->setVecLane(reg, val);
319 }
320 virtual void
321 setVecLane(const RegId &reg,
322 const LaneData<LaneSize::EightByte> &val) override
323 {
324 return actualTC->setVecLane(reg, val);
325 }
271 /** @} */
272
326 /** @} */
327
273 const VecElem& readVecElem(const RegId& reg) const override
274 { return actualTC->readVecElem(reg); }
328 const VecElem &
329 readVecElem(const RegId& reg) const override
330 {
331 return actualTC->readVecElem(reg);
332 }
275
333
276 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override
277 { return actualTC->readVecPredReg(reg); }
334 const VecPredRegContainer &
335 readVecPredReg(const RegId& reg) const override
336 {
337 return actualTC->readVecPredReg(reg);
338 }
278
339
279 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
280 { return actualTC->getWritableVecPredReg(reg); }
340 VecPredRegContainer &
341 getWritableVecPredReg(const RegId& reg) override
342 {
343 return actualTC->getWritableVecPredReg(reg);
344 }
281
345
282 RegVal readCCReg(int reg_idx) override
283 { return actualTC->readCCReg(reg_idx); }
346 RegVal
347 readCCReg(RegIndex reg_idx) const override
348 {
349 return actualTC->readCCReg(reg_idx);
350 }
284
285 void
351
352 void
286 setIntReg(int reg_idx, RegVal val) override
353 setIntReg(RegIndex reg_idx, RegVal val) override
287 {
288 actualTC->setIntReg(reg_idx, val);
289 checkerTC->setIntReg(reg_idx, val);
290 }
291
292 void
354 {
355 actualTC->setIntReg(reg_idx, val);
356 checkerTC->setIntReg(reg_idx, val);
357 }
358
359 void
293 setFloatReg(int reg_idx, RegVal val) override
360 setFloatReg(RegIndex reg_idx, RegVal val) override
294 {
295 actualTC->setFloatReg(reg_idx, val);
296 checkerTC->setFloatReg(reg_idx, val);
297 }
298
299 void
300 setVecReg(const RegId& reg, const VecRegContainer& val) override
301 {

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313 void
314 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
315 {
316 actualTC->setVecPredReg(reg, val);
317 checkerTC->setVecPredReg(reg, val);
318 }
319
320 void
361 {
362 actualTC->setFloatReg(reg_idx, val);
363 checkerTC->setFloatReg(reg_idx, val);
364 }
365
366 void
367 setVecReg(const RegId& reg, const VecRegContainer& val) override
368 {

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380 void
381 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
382 {
383 actualTC->setVecPredReg(reg, val);
384 checkerTC->setVecPredReg(reg, val);
385 }
386
387 void
321 setCCReg(int reg_idx, RegVal val) override
388 setCCReg(RegIndex reg_idx, RegVal val) override
322 {
323 actualTC->setCCReg(reg_idx, val);
324 checkerTC->setCCReg(reg_idx, val);
325 }
326
327 /** Reads this thread's PC state. */
389 {
390 actualTC->setCCReg(reg_idx, val);
391 checkerTC->setCCReg(reg_idx, val);
392 }
393
394 /** Reads this thread's PC state. */
328 TheISA::PCState pcState() override
329 { return actualTC->pcState(); }
395 TheISA::PCState pcState() const override { return actualTC->pcState(); }
330
331 /** Sets this thread's PC state. */
332 void
333 pcState(const TheISA::PCState &val) override
334 {
335 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
336 val, checkerTC->pcState());
337 checkerTC->pcState(val);

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348
349 void
350 pcStateNoRecord(const TheISA::PCState &val) override
351 {
352 return actualTC->pcState(val);
353 }
354
355 /** Reads this thread's PC. */
396
397 /** Sets this thread's PC state. */
398 void
399 pcState(const TheISA::PCState &val) override
400 {
401 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
402 val, checkerTC->pcState());
403 checkerTC->pcState(val);

--- 10 unchanged lines hidden (view full) ---

414
415 void
416 pcStateNoRecord(const TheISA::PCState &val) override
417 {
418 return actualTC->pcState(val);
419 }
420
421 /** Reads this thread's PC. */
356 Addr instAddr() override
357 { return actualTC->instAddr(); }
422 Addr instAddr() const override { return actualTC->instAddr(); }
358
359 /** Reads this thread's next PC. */
423
424 /** Reads this thread's next PC. */
360 Addr nextInstAddr() override
361 { return actualTC->nextInstAddr(); }
425 Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
362
363 /** Reads this thread's next PC. */
426
427 /** Reads this thread's next PC. */
364 MicroPC microPC() override
365 { return actualTC->microPC(); }
428 MicroPC microPC() const override { return actualTC->microPC(); }
366
429
367 RegVal readMiscRegNoEffect(int misc_reg) const override
368 { return actualTC->readMiscRegNoEffect(misc_reg); }
430 RegVal
431 readMiscRegNoEffect(RegIndex misc_reg) const override
432 {
433 return actualTC->readMiscRegNoEffect(misc_reg);
434 }
369
435
370 RegVal readMiscReg(int misc_reg) override
371 { return actualTC->readMiscReg(misc_reg); }
436 RegVal
437 readMiscReg(RegIndex misc_reg) override
438 {
439 return actualTC->readMiscReg(misc_reg);
440 }
372
373 void
441
442 void
374 setMiscRegNoEffect(int misc_reg, RegVal val) override
443 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
375 {
376 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
377 " and O3..\n", misc_reg);
378 checkerTC->setMiscRegNoEffect(misc_reg, val);
379 actualTC->setMiscRegNoEffect(misc_reg, val);
380 }
381
382 void
444 {
445 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
446 " and O3..\n", misc_reg);
447 checkerTC->setMiscRegNoEffect(misc_reg, val);
448 actualTC->setMiscRegNoEffect(misc_reg, val);
449 }
450
451 void
383 setMiscReg(int misc_reg, RegVal val) override
452 setMiscReg(RegIndex misc_reg, RegVal val) override
384 {
385 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
386 " and O3..\n", misc_reg);
387 checkerTC->setMiscReg(misc_reg, val);
388 actualTC->setMiscReg(misc_reg, val);
389 }
390
391 RegId
392 flattenRegId(const RegId& regId) const override
393 {
394 return actualTC->flattenRegId(regId);
395 }
396
453 {
454 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
455 " and O3..\n", misc_reg);
456 checkerTC->setMiscReg(misc_reg, val);
457 actualTC->setMiscReg(misc_reg, val);
458 }
459
460 RegId
461 flattenRegId(const RegId& regId) const override
462 {
463 return actualTC->flattenRegId(regId);
464 }
465
397 unsigned readStCondFailures() override
398 { return actualTC->readStCondFailures(); }
466 unsigned
467 readStCondFailures() const override
468 {
469 return actualTC->readStCondFailures();
470 }
399
400 void
401 setStCondFailures(unsigned sc_failures) override
402 {
403 actualTC->setStCondFailures(sc_failures);
404 }
405
471
472 void
473 setStCondFailures(unsigned sc_failures) override
474 {
475 actualTC->setStCondFailures(sc_failures);
476 }
477
406 Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
478 Counter
479 readFuncExeInst() const override
480 {
481 return actualTC->readFuncExeInst();
482 }
407
483
408 RegVal readIntRegFlat(int idx) override {
484 RegVal
485 readIntRegFlat(RegIndex idx) const override
486 {
409 return actualTC->readIntRegFlat(idx);
410 }
411
412 void
487 return actualTC->readIntRegFlat(idx);
488 }
489
490 void
413 setIntRegFlat(int idx, RegVal val) override
491 setIntRegFlat(RegIndex idx, RegVal val) override
414 {
415 actualTC->setIntRegFlat(idx, val);
416 }
417
418 RegVal
492 {
493 actualTC->setIntRegFlat(idx, val);
494 }
495
496 RegVal
419 readFloatRegFlat(int idx) override
497 readFloatRegFlat(RegIndex idx) const override
420 {
421 return actualTC->readFloatRegFlat(idx);
422 }
423
424 void
498 {
499 return actualTC->readFloatRegFlat(idx);
500 }
501
502 void
425 setFloatRegFlat(int idx, RegVal val) override
503 setFloatRegFlat(RegIndex idx, RegVal val) override
426 {
427 actualTC->setFloatRegFlat(idx, val);
428 }
429
430 const VecRegContainer &
504 {
505 actualTC->setFloatRegFlat(idx, val);
506 }
507
508 const VecRegContainer &
431 readVecRegFlat(int idx) const override
509 readVecRegFlat(RegIndex idx) const override
432 {
433 return actualTC->readVecRegFlat(idx);
434 }
435
436 /**
437 * Read vector register for modification, flat indexing.
438 */
439 VecRegContainer &
510 {
511 return actualTC->readVecRegFlat(idx);
512 }
513
514 /**
515 * Read vector register for modification, flat indexing.
516 */
517 VecRegContainer &
440 getWritableVecRegFlat(int idx) override
518 getWritableVecRegFlat(RegIndex idx) override
441 {
442 return actualTC->getWritableVecRegFlat(idx);
443 }
444
519 {
520 return actualTC->getWritableVecRegFlat(idx);
521 }
522
445 void setVecRegFlat(int idx, const VecRegContainer& val) override
446 { actualTC->setVecRegFlat(idx, val); }
523 void
524 setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
525 {
526 actualTC->setVecRegFlat(idx, val);
527 }
447
528
448 const VecElem& readVecElemFlat(const RegIndex& idx,
449 const ElemIndex& elem_idx) const override
450 { return actualTC->readVecElemFlat(idx, elem_idx); }
529 const VecElem &
530 readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
531 {
532 return actualTC->readVecElemFlat(idx, elem_idx);
533 }
451
534
452 void setVecElemFlat(const RegIndex& idx,
453 const ElemIndex& elem_idx, const VecElem& val) override
454 { actualTC->setVecElemFlat(idx, elem_idx, val); }
535 void
536 setVecElemFlat(RegIndex idx,
537 const ElemIndex& elem_idx, const VecElem& val) override
538 {
539 actualTC->setVecElemFlat(idx, elem_idx, val);
540 }
455
541
456 const VecPredRegContainer& readVecPredRegFlat(int idx) const override
457 { return actualTC->readVecPredRegFlat(idx); }
542 const VecPredRegContainer &
543 readVecPredRegFlat(RegIndex idx) const override
544 {
545 return actualTC->readVecPredRegFlat(idx);
546 }
458
547
459 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override
460 { return actualTC->getWritableVecPredRegFlat(idx); }
548 VecPredRegContainer &
549 getWritableVecPredRegFlat(RegIndex idx) override
550 {
551 return actualTC->getWritableVecPredRegFlat(idx);
552 }
461
553
462 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
463 { actualTC->setVecPredRegFlat(idx, val); }
554 void
555 setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
556 {
557 actualTC->setVecPredRegFlat(idx, val);
558 }
464
559
465 RegVal readCCRegFlat(int idx) override
466 { return actualTC->readCCRegFlat(idx); }
560 RegVal
561 readCCRegFlat(RegIndex idx) const override
562 {
563 return actualTC->readCCRegFlat(idx);
564 }
467
565
468 void setCCRegFlat(int idx, RegVal val) override
469 { actualTC->setCCRegFlat(idx, val); }
566 void
567 setCCRegFlat(RegIndex idx, RegVal val) override
568 {
569 actualTC->setCCRegFlat(idx, val);
570 }
470};
471
472#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
571};
572
573#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__