thread_context.hh (13611:c8b7847b4171) | thread_context.hh (13622:ba31c2a23eca) |
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1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 255 unchanged lines hidden (view full) --- 264 { return actualTC->readVecElem(reg); } 265 266 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 267 { return actualTC->readVecPredReg(reg); } 268 269 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 270 { return actualTC->getWritableVecPredReg(reg); } 271 | 1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 255 unchanged lines hidden (view full) --- 264 { return actualTC->readVecElem(reg); } 265 266 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 267 { return actualTC->readVecPredReg(reg); } 268 269 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 270 { return actualTC->getWritableVecPredReg(reg); } 271 |
272 CCReg readCCReg(int reg_idx) | 272 RegVal readCCReg(int reg_idx) |
273 { return actualTC->readCCReg(reg_idx); } 274 275 void 276 setIntReg(int reg_idx, RegVal val) 277 { 278 actualTC->setIntReg(reg_idx, val); 279 checkerTC->setIntReg(reg_idx, val); 280 } --- 22 unchanged lines hidden (view full) --- 303 void 304 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 305 { 306 actualTC->setVecPredReg(reg, val); 307 checkerTC->setVecPredReg(reg, val); 308 } 309 310 void | 273 { return actualTC->readCCReg(reg_idx); } 274 275 void 276 setIntReg(int reg_idx, RegVal val) 277 { 278 actualTC->setIntReg(reg_idx, val); 279 checkerTC->setIntReg(reg_idx, val); 280 } --- 22 unchanged lines hidden (view full) --- 303 void 304 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 305 { 306 actualTC->setVecPredReg(reg, val); 307 checkerTC->setVecPredReg(reg, val); 308 } 309 310 void |
311 setCCReg(int reg_idx, CCReg val) | 311 setCCReg(int reg_idx, RegVal val) |
312 { 313 actualTC->setCCReg(reg_idx, val); 314 checkerTC->setCCReg(reg_idx, val); 315 } 316 317 /** Reads this thread's PC state. */ 318 TheISA::PCState pcState() 319 { return actualTC->pcState(); } --- 125 unchanged lines hidden (view full) --- 445 { return actualTC->readVecPredRegFlat(idx); } 446 447 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 448 { return actualTC->getWritableVecPredRegFlat(idx); } 449 450 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 451 { actualTC->setVecPredRegFlat(idx, val); } 452 | 312 { 313 actualTC->setCCReg(reg_idx, val); 314 checkerTC->setCCReg(reg_idx, val); 315 } 316 317 /** Reads this thread's PC state. */ 318 TheISA::PCState pcState() 319 { return actualTC->pcState(); } --- 125 unchanged lines hidden (view full) --- 445 { return actualTC->readVecPredRegFlat(idx); } 446 447 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 448 { return actualTC->getWritableVecPredRegFlat(idx); } 449 450 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 451 { actualTC->setVecPredRegFlat(idx, val); } 452 |
453 CCReg readCCRegFlat(int idx) | 453 RegVal readCCRegFlat(int idx) |
454 { return actualTC->readCCRegFlat(idx); } 455 | 454 { return actualTC->readCCRegFlat(idx); } 455 |
456 void setCCRegFlat(int idx, CCReg val) | 456 void setCCRegFlat(int idx, RegVal val) |
457 { actualTC->setCCRegFlat(idx, val); } 458}; 459 460#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ | 457 { actualTC->setCCRegFlat(idx, val); } 458}; 459 460#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |