thread_context.hh (13582:989577bf6abc) | thread_context.hh (13610:5d5404ac6288) |
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1/* | 1/* |
2 * Copyright (c) 2011-2012, 2016 ARM Limited | 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 247 unchanged lines hidden (view full) --- 258 virtual void setVecLane(const RegId& reg, 259 const LaneData<LaneSize::EightByte>& val) 260 { return actualTC->setVecLane(reg, val); } 261 /** @} */ 262 263 const VecElem& readVecElem(const RegId& reg) const 264 { return actualTC->readVecElem(reg); } 265 | 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 247 unchanged lines hidden (view full) --- 258 virtual void setVecLane(const RegId& reg, 259 const LaneData<LaneSize::EightByte>& val) 260 { return actualTC->setVecLane(reg, val); } 261 /** @} */ 262 263 const VecElem& readVecElem(const RegId& reg) const 264 { return actualTC->readVecElem(reg); } 265 |
266 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 267 { return actualTC->readVecPredReg(reg); } 268 269 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 270 { return actualTC->getWritableVecPredReg(reg); } 271 |
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266 CCReg readCCReg(int reg_idx) 267 { return actualTC->readCCReg(reg_idx); } 268 269 void 270 setIntReg(int reg_idx, RegVal val) 271 { 272 actualTC->setIntReg(reg_idx, val); 273 checkerTC->setIntReg(reg_idx, val); --- 16 unchanged lines hidden (view full) --- 290 void 291 setVecElem(const RegId& reg, const VecElem& val) 292 { 293 actualTC->setVecElem(reg, val); 294 checkerTC->setVecElem(reg, val); 295 } 296 297 void | 272 CCReg readCCReg(int reg_idx) 273 { return actualTC->readCCReg(reg_idx); } 274 275 void 276 setIntReg(int reg_idx, RegVal val) 277 { 278 actualTC->setIntReg(reg_idx, val); 279 checkerTC->setIntReg(reg_idx, val); --- 16 unchanged lines hidden (view full) --- 296 void 297 setVecElem(const RegId& reg, const VecElem& val) 298 { 299 actualTC->setVecElem(reg, val); 300 checkerTC->setVecElem(reg, val); 301 } 302 303 void |
304 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 305 { 306 actualTC->setVecPredReg(reg, val); 307 checkerTC->setVecPredReg(reg, val); 308 } 309 310 void |
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298 setCCReg(int reg_idx, CCReg val) 299 { 300 actualTC->setCCReg(reg_idx, val); 301 checkerTC->setCCReg(reg_idx, val); 302 } 303 304 /** Reads this thread's PC state. */ 305 TheISA::PCState pcState() --- 117 unchanged lines hidden (view full) --- 423 const VecElem& readVecElemFlat(const RegIndex& idx, 424 const ElemIndex& elem_idx) const 425 { return actualTC->readVecElemFlat(idx, elem_idx); } 426 427 void setVecElemFlat(const RegIndex& idx, 428 const ElemIndex& elem_idx, const VecElem& val) 429 { actualTC->setVecElemFlat(idx, elem_idx, val); } 430 | 311 setCCReg(int reg_idx, CCReg val) 312 { 313 actualTC->setCCReg(reg_idx, val); 314 checkerTC->setCCReg(reg_idx, val); 315 } 316 317 /** Reads this thread's PC state. */ 318 TheISA::PCState pcState() --- 117 unchanged lines hidden (view full) --- 436 const VecElem& readVecElemFlat(const RegIndex& idx, 437 const ElemIndex& elem_idx) const 438 { return actualTC->readVecElemFlat(idx, elem_idx); } 439 440 void setVecElemFlat(const RegIndex& idx, 441 const ElemIndex& elem_idx, const VecElem& val) 442 { actualTC->setVecElemFlat(idx, elem_idx, val); } 443 |
444 const VecPredRegContainer& readVecPredRegFlat(int idx) const override 445 { return actualTC->readVecPredRegFlat(idx); } 446 447 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 448 { return actualTC->getWritableVecPredRegFlat(idx); } 449 450 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 451 { actualTC->setVecPredRegFlat(idx, val); } 452 |
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431 CCReg readCCRegFlat(int idx) 432 { return actualTC->readCCRegFlat(idx); } 433 434 void setCCRegFlat(int idx, CCReg val) 435 { actualTC->setCCRegFlat(idx, val); } 436}; 437 438#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ | 453 CCReg readCCRegFlat(int idx) 454 { return actualTC->readCCRegFlat(idx); } 455 456 void setCCRegFlat(int idx, CCReg val) 457 { actualTC->setCCRegFlat(idx, val); } 458}; 459 460#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |