thread_context.hh (13557:fc33e6048b25) thread_context.hh (13582:989577bf6abc)
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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343
344 RegVal readMiscRegNoEffect(int misc_reg) const
345 { return actualTC->readMiscRegNoEffect(misc_reg); }
346
347 RegVal readMiscReg(int misc_reg)
348 { return actualTC->readMiscReg(misc_reg); }
349
350 void
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 334 unchanged lines hidden (view full) ---

343
344 RegVal readMiscRegNoEffect(int misc_reg) const
345 { return actualTC->readMiscRegNoEffect(misc_reg); }
346
347 RegVal readMiscReg(int misc_reg)
348 { return actualTC->readMiscReg(misc_reg); }
349
350 void
351 setMiscRegNoEffect(int misc_reg, const RegVal &val)
351 setMiscRegNoEffect(int misc_reg, RegVal val)
352 {
353 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
354 " and O3..\n", misc_reg);
355 checkerTC->setMiscRegNoEffect(misc_reg, val);
356 actualTC->setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
352 {
353 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
354 " and O3..\n", misc_reg);
355 checkerTC->setMiscRegNoEffect(misc_reg, val);
356 actualTC->setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
360 setMiscReg(int misc_reg, const RegVal &val)
360 setMiscReg(int misc_reg, RegVal val)
361 {
362 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
363 " and O3..\n", misc_reg);
364 checkerTC->setMiscReg(misc_reg, val);
365 actualTC->setMiscReg(misc_reg, val);
366 }
367
368 RegId

--- 70 unchanged lines hidden --- 		361 {
362 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
363 " and O3..\n", misc_reg);
364 checkerTC->setMiscReg(misc_reg, val);
365 actualTC->setMiscReg(misc_reg, val);
366 }
367
368 RegId

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