thread_context.hh (13500:6e0a2a7c6d8c) thread_context.hh (13557:fc33e6048b25)
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 192 unchanged lines hidden (view full) ---

201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 192 unchanged lines hidden (view full) ---

201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
209 uint64_t readIntReg(int reg_idx)
210 { return actualTC->readIntReg(reg_idx); }
209 RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
211
210
212 FloatRegBits readFloatRegBits(int reg_idx)
213 { return actualTC->readFloatRegBits(reg_idx); }
211 RegVal
212 readFloatRegBits(int reg_idx)
213 {
214 return actualTC->readFloatRegBits(reg_idx);
215 }
214
215 const VecRegContainer& readVecReg(const RegId& reg) const
216 { return actualTC->readVecReg(reg); }
217
218 /**
219 * Read vector register for modification, hierarchical indexing.
220 */
221 VecRegContainer& getWritableVecReg(const RegId& reg)

--- 37 unchanged lines hidden (view full) ---

259 /** @} */
260
261 const VecElem& readVecElem(const RegId& reg) const
262 { return actualTC->readVecElem(reg); }
263
264 CCReg readCCReg(int reg_idx)
265 { return actualTC->readCCReg(reg_idx); }
266
216
217 const VecRegContainer& readVecReg(const RegId& reg) const
218 { return actualTC->readVecReg(reg); }
219
220 /**
221 * Read vector register for modification, hierarchical indexing.
222 */
223 VecRegContainer& getWritableVecReg(const RegId& reg)

--- 37 unchanged lines hidden (view full) ---

261 /** @} */
262
263 const VecElem& readVecElem(const RegId& reg) const
264 { return actualTC->readVecElem(reg); }
265
266 CCReg readCCReg(int reg_idx)
267 { return actualTC->readCCReg(reg_idx); }
268
267 void setIntReg(int reg_idx, uint64_t val)
269 void
270 setIntReg(int reg_idx, RegVal val)
268 {
269 actualTC->setIntReg(reg_idx, val);
270 checkerTC->setIntReg(reg_idx, val);
271 }
272
271 {
272 actualTC->setIntReg(reg_idx, val);
273 checkerTC->setIntReg(reg_idx, val);
274 }
275
273 void setFloatRegBits(int reg_idx, FloatRegBits val)
276 void
277 setFloatRegBits(int reg_idx, RegVal val)
274 {
275 actualTC->setFloatRegBits(reg_idx, val);
276 checkerTC->setFloatRegBits(reg_idx, val);
277 }
278
278 {
279 actualTC->setFloatRegBits(reg_idx, val);
280 checkerTC->setFloatRegBits(reg_idx, val);
281 }
282
279 void setVecReg(const RegId& reg, const VecRegContainer& val)
283 void
284 setVecReg(const RegId& reg, const VecRegContainer& val)
280 {
281 actualTC->setVecReg(reg, val);
282 checkerTC->setVecReg(reg, val);
283 }
284
285 {
286 actualTC->setVecReg(reg, val);
287 checkerTC->setVecReg(reg, val);
288 }
289
285 void setVecElem(const RegId& reg, const VecElem& val)
290 void
291 setVecElem(const RegId& reg, const VecElem& val)
286 {
287 actualTC->setVecElem(reg, val);
288 checkerTC->setVecElem(reg, val);
289 }
290
292 {
293 actualTC->setVecElem(reg, val);
294 checkerTC->setVecElem(reg, val);
295 }
296
291 void setCCReg(int reg_idx, CCReg val)
297 void
298 setCCReg(int reg_idx, CCReg val)
292 {
293 actualTC->setCCReg(reg_idx, val);
294 checkerTC->setCCReg(reg_idx, val);
295 }
296
297 /** Reads this thread's PC state. */
298 TheISA::PCState pcState()
299 { return actualTC->pcState(); }
300
301 /** Sets this thread's PC state. */
299 {
300 actualTC->setCCReg(reg_idx, val);
301 checkerTC->setCCReg(reg_idx, val);
302 }
303
304 /** Reads this thread's PC state. */
305 TheISA::PCState pcState()
306 { return actualTC->pcState(); }
307
308 /** Sets this thread's PC state. */
302 void pcState(const TheISA::PCState &val)
309 void
310 pcState(const TheISA::PCState &val)
303 {
304 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
305 val, checkerTC->pcState());
306 checkerTC->pcState(val);
307 checkerCPU->recordPCChange(val);
308 return actualTC->pcState(val);
309 }
310
311 {
312 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
313 val, checkerTC->pcState());
314 checkerTC->pcState(val);
315 checkerCPU->recordPCChange(val);
316 return actualTC->pcState(val);
317 }
318
311 void setNPC(Addr val)
319 void
320 setNPC(Addr val)
312 {
313 checkerTC->setNPC(val);
314 actualTC->setNPC(val);
315 }
316
321 {
322 checkerTC->setNPC(val);
323 actualTC->setNPC(val);
324 }
325
317 void pcStateNoRecord(const TheISA::PCState &val)
326 void
327 pcStateNoRecord(const TheISA::PCState &val)
318 {
319 return actualTC->pcState(val);
320 }
321
322 /** Reads this thread's PC. */
323 Addr instAddr()
324 { return actualTC->instAddr(); }
325
326 /** Reads this thread's next PC. */
327 Addr nextInstAddr()
328 { return actualTC->nextInstAddr(); }
329
330 /** Reads this thread's next PC. */
331 MicroPC microPC()
332 { return actualTC->microPC(); }
333
328 {
329 return actualTC->pcState(val);
330 }
331
332 /** Reads this thread's PC. */
333 Addr instAddr()
334 { return actualTC->instAddr(); }
335
336 /** Reads this thread's next PC. */
337 Addr nextInstAddr()
338 { return actualTC->nextInstAddr(); }
339
340 /** Reads this thread's next PC. */
341 MicroPC microPC()
342 { return actualTC->microPC(); }
343
334 MiscReg readMiscRegNoEffect(int misc_reg) const
344 RegVal readMiscRegNoEffect(int misc_reg) const
335 { return actualTC->readMiscRegNoEffect(misc_reg); }
336
345 { return actualTC->readMiscRegNoEffect(misc_reg); }
346
337 MiscReg readMiscReg(int misc_reg)
347 RegVal readMiscReg(int misc_reg)
338 { return actualTC->readMiscReg(misc_reg); }
339
348 { return actualTC->readMiscReg(misc_reg); }
349
340 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
350 void
351 setMiscRegNoEffect(int misc_reg, const RegVal &val)
341 {
342 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
343 " and O3..\n", misc_reg);
344 checkerTC->setMiscRegNoEffect(misc_reg, val);
345 actualTC->setMiscRegNoEffect(misc_reg, val);
346 }
347
352 {
353 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
354 " and O3..\n", misc_reg);
355 checkerTC->setMiscRegNoEffect(misc_reg, val);
356 actualTC->setMiscRegNoEffect(misc_reg, val);
357 }
358
348 void setMiscReg(int misc_reg, const MiscReg &val)
359 void
360 setMiscReg(int misc_reg, const RegVal &val)
349 {
350 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
351 " and O3..\n", misc_reg);
352 checkerTC->setMiscReg(misc_reg, val);
353 actualTC->setMiscReg(misc_reg, val);
354 }
355
361 {
362 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
363 " and O3..\n", misc_reg);
364 checkerTC->setMiscReg(misc_reg, val);
365 actualTC->setMiscReg(misc_reg, val);
366 }
367
356 RegId flattenRegId(const RegId& regId) const {
368 RegId
369 flattenRegId(const RegId& regId) const
370 {
357 return actualTC->flattenRegId(regId);
358 }
359
360 unsigned readStCondFailures()
361 { return actualTC->readStCondFailures(); }
362
371 return actualTC->flattenRegId(regId);
372 }
373
374 unsigned readStCondFailures()
375 { return actualTC->readStCondFailures(); }
376
363 void setStCondFailures(unsigned sc_failures)
377 void
378 setStCondFailures(unsigned sc_failures)
364 {
365 actualTC->setStCondFailures(sc_failures);
366 }
367
368 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
369
379 {
380 actualTC->setStCondFailures(sc_failures);
381 }
382
383 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
384
370 uint64_t readIntRegFlat(int idx)
371 { return actualTC->readIntRegFlat(idx); }
385 RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
372
386
373 void setIntRegFlat(int idx, uint64_t val)
374 { actualTC->setIntRegFlat(idx, val); }
387 void
388 setIntRegFlat(int idx, RegVal val)
389 {
390 actualTC->setIntRegFlat(idx, val);
391 }
375
392
376 FloatRegBits readFloatRegBitsFlat(int idx)
377 { return actualTC->readFloatRegBitsFlat(idx); }
393 RegVal
394 readFloatRegBitsFlat(int idx)
395 {
396 return actualTC->readFloatRegBitsFlat(idx);
397 }
378
398
379 void setFloatRegBitsFlat(int idx, FloatRegBits val)
380 { actualTC->setFloatRegBitsFlat(idx, val); }
399 void
400 setFloatRegBitsFlat(int idx, RegVal val)
401 {
402 actualTC->setFloatRegBitsFlat(idx, val);
403 }
381
404
382 const VecRegContainer& readVecRegFlat(int idx) const
383 { return actualTC->readVecRegFlat(idx); }
405 const VecRegContainer &
406 readVecRegFlat(int idx) const
407 {
408 return actualTC->readVecRegFlat(idx);
409 }
384
385 /**
386 * Read vector register for modification, flat indexing.
387 */
410
411 /**
412 * Read vector register for modification, flat indexing.
413 */
388 VecRegContainer& getWritableVecRegFlat(int idx)
389 { return actualTC->getWritableVecRegFlat(idx); }
414 VecRegContainer &
415 getWritableVecRegFlat(int idx)
416 {
417 return actualTC->getWritableVecRegFlat(idx);
418 }
390
391 void setVecRegFlat(int idx, const VecRegContainer& val)
392 { actualTC->setVecRegFlat(idx, val); }
393
394 const VecElem& readVecElemFlat(const RegIndex& idx,
395 const ElemIndex& elem_idx) const
396 { return actualTC->readVecElemFlat(idx, elem_idx); }
397

--- 12 unchanged lines hidden --- 		419
420 void setVecRegFlat(int idx, const VecRegContainer& val)
421 { actualTC->setVecRegFlat(idx, val); }
422
423 const VecElem& readVecElemFlat(const RegIndex& idx,
424 const ElemIndex& elem_idx) const
425 { return actualTC->readVecElemFlat(idx, elem_idx); }
426

--- 12 unchanged lines hidden ---