thread_context.hh (12106:7784fac1b159) | thread_context.hh (12109:f29e9c5418aa) |
---|---|
1/* | 1/* |
2 * Copyright (c) 2011-2012 ARM Limited | 2 * Copyright (c) 2011-2012, 2016 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 199 unchanged lines hidden (view full) --- 210 { return actualTC->readIntReg(reg_idx); } 211 212 FloatReg readFloatReg(int reg_idx) 213 { return actualTC->readFloatReg(reg_idx); } 214 215 FloatRegBits readFloatRegBits(int reg_idx) 216 { return actualTC->readFloatRegBits(reg_idx); } 217 | 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 199 unchanged lines hidden (view full) --- 210 { return actualTC->readIntReg(reg_idx); } 211 212 FloatReg readFloatReg(int reg_idx) 213 { return actualTC->readFloatReg(reg_idx); } 214 215 FloatRegBits readFloatRegBits(int reg_idx) 216 { return actualTC->readFloatRegBits(reg_idx); } 217 |
218 const VecRegContainer& readVecReg(const RegId& reg) const 219 { return actualTC->readVecReg(reg); } 220 221 /** 222 * Read vector register for modification, hierarchical indexing. 223 */ 224 VecRegContainer& getWritableVecReg(const RegId& reg) 225 { return actualTC->getWritableVecReg(reg); } 226 227 /** Vector Register Lane Interfaces. */ 228 /** @{ */ 229 /** Reads source vector 8bit operand. */ 230 ConstVecLane8 231 readVec8BitLaneReg(const RegId& reg) const 232 { return actualTC->readVec8BitLaneReg(reg); } 233 234 /** Reads source vector 16bit operand. */ 235 ConstVecLane16 236 readVec16BitLaneReg(const RegId& reg) const 237 { return actualTC->readVec16BitLaneReg(reg); } 238 239 /** Reads source vector 32bit operand. */ 240 ConstVecLane32 241 readVec32BitLaneReg(const RegId& reg) const 242 { return actualTC->readVec32BitLaneReg(reg); } 243 244 /** Reads source vector 64bit operand. */ 245 ConstVecLane64 246 readVec64BitLaneReg(const RegId& reg) const 247 { return actualTC->readVec64BitLaneReg(reg); } 248 249 /** Write a lane of the destination vector register. */ 250 virtual void setVecLane(const RegId& reg, 251 const LaneData<LaneSize::Byte>& val) 252 { return actualTC->setVecLane(reg, val); } 253 virtual void setVecLane(const RegId& reg, 254 const LaneData<LaneSize::TwoByte>& val) 255 { return actualTC->setVecLane(reg, val); } 256 virtual void setVecLane(const RegId& reg, 257 const LaneData<LaneSize::FourByte>& val) 258 { return actualTC->setVecLane(reg, val); } 259 virtual void setVecLane(const RegId& reg, 260 const LaneData<LaneSize::EightByte>& val) 261 { return actualTC->setVecLane(reg, val); } 262 /** @} */ 263 264 const VecElem& readVecElem(const RegId& reg) const 265 { return actualTC->readVecElem(reg); } 266 |
|
218 CCReg readCCReg(int reg_idx) 219 { return actualTC->readCCReg(reg_idx); } 220 221 void setIntReg(int reg_idx, uint64_t val) 222 { 223 actualTC->setIntReg(reg_idx, val); 224 checkerTC->setIntReg(reg_idx, val); 225 } --- 5 unchanged lines hidden (view full) --- 231 } 232 233 void setFloatRegBits(int reg_idx, FloatRegBits val) 234 { 235 actualTC->setFloatRegBits(reg_idx, val); 236 checkerTC->setFloatRegBits(reg_idx, val); 237 } 238 | 267 CCReg readCCReg(int reg_idx) 268 { return actualTC->readCCReg(reg_idx); } 269 270 void setIntReg(int reg_idx, uint64_t val) 271 { 272 actualTC->setIntReg(reg_idx, val); 273 checkerTC->setIntReg(reg_idx, val); 274 } --- 5 unchanged lines hidden (view full) --- 280 } 281 282 void setFloatRegBits(int reg_idx, FloatRegBits val) 283 { 284 actualTC->setFloatRegBits(reg_idx, val); 285 checkerTC->setFloatRegBits(reg_idx, val); 286 } 287 |
288 void setVecReg(const RegId& reg, const VecRegContainer& val) 289 { 290 actualTC->setVecReg(reg, val); 291 checkerTC->setVecReg(reg, val); 292 } 293 294 void setVecElem(const RegId& reg, const VecElem& val) 295 { 296 actualTC->setVecElem(reg, val); 297 checkerTC->setVecElem(reg, val); 298 } 299 |
|
239 void setCCReg(int reg_idx, CCReg val) 240 { 241 actualTC->setCCReg(reg_idx, val); 242 checkerTC->setCCReg(reg_idx, val); 243 } 244 245 /** Reads this thread's PC state. */ 246 TheISA::PCState pcState() --- 81 unchanged lines hidden (view full) --- 328 { actualTC->setFloatRegFlat(idx, val); } 329 330 FloatRegBits readFloatRegBitsFlat(int idx) 331 { return actualTC->readFloatRegBitsFlat(idx); } 332 333 void setFloatRegBitsFlat(int idx, FloatRegBits val) 334 { actualTC->setFloatRegBitsFlat(idx, val); } 335 | 300 void setCCReg(int reg_idx, CCReg val) 301 { 302 actualTC->setCCReg(reg_idx, val); 303 checkerTC->setCCReg(reg_idx, val); 304 } 305 306 /** Reads this thread's PC state. */ 307 TheISA::PCState pcState() --- 81 unchanged lines hidden (view full) --- 389 { actualTC->setFloatRegFlat(idx, val); } 390 391 FloatRegBits readFloatRegBitsFlat(int idx) 392 { return actualTC->readFloatRegBitsFlat(idx); } 393 394 void setFloatRegBitsFlat(int idx, FloatRegBits val) 395 { actualTC->setFloatRegBitsFlat(idx, val); } 396 |
397 const VecRegContainer& readVecRegFlat(int idx) const 398 { return actualTC->readVecRegFlat(idx); } 399 400 /** 401 * Read vector register for modification, flat indexing. 402 */ 403 VecRegContainer& getWritableVecRegFlat(int idx) 404 { return actualTC->getWritableVecRegFlat(idx); } 405 406 void setVecRegFlat(int idx, const VecRegContainer& val) 407 { actualTC->setVecRegFlat(idx, val); } 408 409 const VecElem& readVecElemFlat(const RegIndex& idx, 410 const ElemIndex& elem_idx) const 411 { return actualTC->readVecElemFlat(idx, elem_idx); } 412 413 void setVecElemFlat(const RegIndex& idx, 414 const ElemIndex& elem_idx, const VecElem& val) 415 { actualTC->setVecElemFlat(idx, elem_idx, val); } 416 |
|
336 CCReg readCCRegFlat(int idx) 337 { return actualTC->readCCRegFlat(idx); } 338 339 void setCCRegFlat(int idx, CCReg val) 340 { actualTC->setCCRegFlat(idx, val); } 341}; 342 343#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ | 417 CCReg readCCRegFlat(int idx) 418 { return actualTC->readCCRegFlat(idx); } 419 420 void setCCRegFlat(int idx, CCReg val) 421 { actualTC->setCCRegFlat(idx, val); } 422}; 423 424#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |