thread_context.hh (10934:5af8f40d8f2c) | thread_context.hh (10935:acd48ddd725f) |
---|---|
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 202 unchanged lines hidden (view full) --- 211 { return actualTC->readFloatReg(reg_idx); } 212 213 FloatRegBits readFloatRegBits(int reg_idx) 214 { return actualTC->readFloatRegBits(reg_idx); } 215 216 CCReg readCCReg(int reg_idx) 217 { return actualTC->readCCReg(reg_idx); } 218 | 1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 202 unchanged lines hidden (view full) --- 211 { return actualTC->readFloatReg(reg_idx); } 212 213 FloatRegBits readFloatRegBits(int reg_idx) 214 { return actualTC->readFloatRegBits(reg_idx); } 215 216 CCReg readCCReg(int reg_idx) 217 { return actualTC->readCCReg(reg_idx); } 218 |
219 const VectorReg &readVectorReg(int reg_idx) 220 { return actualTC->readVectorReg(reg_idx); } 221 | |
222 void setIntReg(int reg_idx, uint64_t val) 223 { 224 actualTC->setIntReg(reg_idx, val); 225 checkerTC->setIntReg(reg_idx, val); 226 } 227 228 void setFloatReg(int reg_idx, FloatReg val) 229 { --- 8 unchanged lines hidden (view full) --- 238 } 239 240 void setCCReg(int reg_idx, CCReg val) 241 { 242 actualTC->setCCReg(reg_idx, val); 243 checkerTC->setCCReg(reg_idx, val); 244 } 245 | 219 void setIntReg(int reg_idx, uint64_t val) 220 { 221 actualTC->setIntReg(reg_idx, val); 222 checkerTC->setIntReg(reg_idx, val); 223 } 224 225 void setFloatReg(int reg_idx, FloatReg val) 226 { --- 8 unchanged lines hidden (view full) --- 235 } 236 237 void setCCReg(int reg_idx, CCReg val) 238 { 239 actualTC->setCCReg(reg_idx, val); 240 checkerTC->setCCReg(reg_idx, val); 241 } 242 |
246 void setVectorReg(int reg_idx, const VectorReg &val) 247 { 248 actualTC->setVectorReg(reg_idx, val); 249 checkerTC->setVectorReg(reg_idx, val); 250 } 251 | |
252 /** Reads this thread's PC state. */ 253 TheISA::PCState pcState() 254 { return actualTC->pcState(); } 255 256 /** Sets this thread's PC state. */ 257 void pcState(const TheISA::PCState &val) 258 { 259 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", --- 40 unchanged lines hidden (view full) --- 300 " and O3..\n", misc_reg); 301 checkerTC->setMiscReg(misc_reg, val); 302 actualTC->setMiscReg(misc_reg, val); 303 } 304 305 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 306 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 307 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } | 243 /** Reads this thread's PC state. */ 244 TheISA::PCState pcState() 245 { return actualTC->pcState(); } 246 247 /** Sets this thread's PC state. */ 248 void pcState(const TheISA::PCState &val) 249 { 250 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", --- 40 unchanged lines hidden (view full) --- 291 " and O3..\n", misc_reg); 292 checkerTC->setMiscReg(misc_reg, val); 293 actualTC->setMiscReg(misc_reg, val); 294 } 295 296 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 297 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 298 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } |
308 int flattenVectorIndex(int reg) { return actualTC->flattenVectorIndex(reg); } | |
309 int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } 310 311 unsigned readStCondFailures() 312 { return actualTC->readStCondFailures(); } 313 314 void setStCondFailures(unsigned sc_failures) 315 { 316 actualTC->setStCondFailures(sc_failures); --- 19 unchanged lines hidden (view full) --- 336 void setFloatRegBitsFlat(int idx, FloatRegBits val) 337 { actualTC->setFloatRegBitsFlat(idx, val); } 338 339 CCReg readCCRegFlat(int idx) 340 { return actualTC->readCCRegFlat(idx); } 341 342 void setCCRegFlat(int idx, CCReg val) 343 { actualTC->setCCRegFlat(idx, val); } | 299 int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } 300 301 unsigned readStCondFailures() 302 { return actualTC->readStCondFailures(); } 303 304 void setStCondFailures(unsigned sc_failures) 305 { 306 actualTC->setStCondFailures(sc_failures); --- 19 unchanged lines hidden (view full) --- 326 void setFloatRegBitsFlat(int idx, FloatRegBits val) 327 { actualTC->setFloatRegBitsFlat(idx, val); } 328 329 CCReg readCCRegFlat(int idx) 330 { return actualTC->readCCRegFlat(idx); } 331 332 void setCCRegFlat(int idx, CCReg val) 333 { actualTC->setCCRegFlat(idx, val); } |
344 345 const VectorReg &readVectorRegFlat(int idx) 346 { return actualTC->readVectorRegFlat(idx); } 347 348 void setVectorRegFlat(int idx, const VectorReg &val) 349 { actualTC->setVectorRegFlat(idx, val); } | |
350}; 351 352#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ | 334}; 335 336#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |