1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 84 unchanged lines hidden (view full) --- 93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); } 94 95 uint32_t socketId() const override { return actualTC->socketId(); } 96 97 int cpuId() const override { return actualTC->cpuId(); } 98 99 ContextID contextId() const override { return actualTC->contextId(); } 100 |
101 void 102 setContextId(ContextID id) override |
103 { 104 actualTC->setContextId(id); 105 checkerTC->setContextId(id); 106 } 107 108 /** Returns this thread's ID number. */ 109 int threadId() const override { return actualTC->threadId(); } |
110 void 111 setThreadId(int id) override |
112 { 113 checkerTC->setThreadId(id); 114 actualTC->setThreadId(id); 115 } 116 117 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); } 118 119 BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); } 120 |
121 CheckerCPU * 122 getCheckerCpuPtr() override |
123 { 124 return checkerCPU; 125 } 126 127 TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); } 128 |
129 TheISA::Decoder * 130 getDecoderPtr() override 131 { |
132 return actualTC->getDecoderPtr(); 133 } 134 135 System *getSystemPtr() override { return actualTC->getSystemPtr(); } 136 |
137 TheISA::Kernel::Statistics * 138 getKernelStats() override 139 { 140 return actualTC->getKernelStats(); 141 } |
142 143 Process *getProcessPtr() override { return actualTC->getProcessPtr(); } 144 145 void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); } 146 147 PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); } 148 |
149 FSTranslatingPortProxy & 150 getVirtProxy() override 151 { 152 return actualTC->getVirtProxy(); 153 } |
154 |
155 void 156 initMemProxies(ThreadContext *tc) override 157 { 158 actualTC->initMemProxies(tc); 159 } |
160 |
161 void 162 connectMemPorts(ThreadContext *tc) |
163 { 164 actualTC->connectMemPorts(tc); 165 } 166 |
167 SETranslatingPortProxy & 168 getMemProxy() override 169 { |
170 return actualTC->getMemProxy(); 171 } 172 173 /** Executes a syscall in SE mode. */ |
174 void 175 syscall(int64_t callnum, Fault *fault) override 176 { 177 return actualTC->syscall(callnum, fault); 178 } |
179 180 Status status() const override { return actualTC->status(); } 181 |
182 void 183 setStatus(Status new_status) override |
184 { 185 actualTC->setStatus(new_status); 186 checkerTC->setStatus(new_status); 187 } 188 189 /// Set the status to Active. 190 void activate() override { actualTC->activate(); } 191 192 /// Set the status to Suspended. |
193 void suspend() override { actualTC->suspend(); } |
194 195 /// Set the status to Halted. |
196 void halt() override { actualTC->halt(); } |
197 |
198 void dumpFuncProfile() override { actualTC->dumpFuncProfile(); } |
199 |
200 void 201 takeOverFrom(ThreadContext *oldContext) override |
202 { 203 actualTC->takeOverFrom(oldContext); 204 checkerTC->copyState(oldContext); 205 } 206 |
207 void 208 regStats(const std::string &name) override |
209 { 210 actualTC->regStats(name); 211 checkerTC->regStats(name); 212 } 213 |
214 EndQuiesceEvent * 215 getQuiesceEvent() override 216 { |
217 return actualTC->getQuiesceEvent(); 218 } 219 |
220 Tick readLastActivate() override { return actualTC->readLastActivate(); } 221 Tick readLastSuspend() override { return actualTC->readLastSuspend(); } |
222 |
223 void profileClear() override { return actualTC->profileClear(); } 224 void profileSample() override { return actualTC->profileSample(); } |
225 226 // @todo: Do I need this? |
227 void 228 copyArchRegs(ThreadContext *tc) override |
229 { 230 actualTC->copyArchRegs(tc); 231 checkerTC->copyArchRegs(tc); 232 } 233 |
234 void 235 clearArchRegs() override |
236 { 237 actualTC->clearArchRegs(); 238 checkerTC->clearArchRegs(); 239 } 240 241 // 242 // New accessors for new decoder. 243 // |
244 RegVal 245 readIntReg(RegIndex reg_idx) const override 246 { |
247 return actualTC->readIntReg(reg_idx); 248 } 249 250 RegVal |
251 readFloatReg(RegIndex reg_idx) const override |
252 { 253 return actualTC->readFloatReg(reg_idx); 254 } 255 |
256 const VecRegContainer & 257 readVecReg (const RegId ®) const override 258 { 259 return actualTC->readVecReg(reg); 260 } |
261 262 /** 263 * Read vector register for modification, hierarchical indexing. 264 */ |
265 VecRegContainer & 266 getWritableVecReg (const RegId ®) override 267 { 268 return actualTC->getWritableVecReg(reg); 269 } |
270 271 /** Vector Register Lane Interfaces. */ 272 /** @{ */ 273 /** Reads source vector 8bit operand. */ 274 ConstVecLane8 |
275 readVec8BitLaneReg(const RegId ®) const override 276 { 277 return actualTC->readVec8BitLaneReg(reg); 278 } |
279 280 /** Reads source vector 16bit operand. */ 281 ConstVecLane16 |
282 readVec16BitLaneReg(const RegId ®) const override 283 { 284 return actualTC->readVec16BitLaneReg(reg); 285 } |
286 287 /** Reads source vector 32bit operand. */ 288 ConstVecLane32 |
289 readVec32BitLaneReg(const RegId ®) const override 290 { 291 return actualTC->readVec32BitLaneReg(reg); 292 } |
293 294 /** Reads source vector 64bit operand. */ 295 ConstVecLane64 |
296 readVec64BitLaneReg(const RegId ®) const override 297 { 298 return actualTC->readVec64BitLaneReg(reg); 299 } |
300 301 /** Write a lane of the destination vector register. */ |
302 virtual void 303 setVecLane(const RegId ®, 304 const LaneData<LaneSize::Byte> &val) override 305 { 306 return actualTC->setVecLane(reg, val); 307 } 308 virtual void 309 setVecLane(const RegId ®, 310 const LaneData<LaneSize::TwoByte> &val) override 311 { 312 return actualTC->setVecLane(reg, val); 313 } 314 virtual void 315 setVecLane(const RegId ®, 316 const LaneData<LaneSize::FourByte> &val) override 317 { 318 return actualTC->setVecLane(reg, val); 319 } 320 virtual void 321 setVecLane(const RegId ®, 322 const LaneData<LaneSize::EightByte> &val) override 323 { 324 return actualTC->setVecLane(reg, val); 325 } |
326 /** @} */ 327 |
328 const VecElem & 329 readVecElem(const RegId& reg) const override 330 { 331 return actualTC->readVecElem(reg); 332 } |
333 |
334 const VecPredRegContainer & 335 readVecPredReg(const RegId& reg) const override 336 { 337 return actualTC->readVecPredReg(reg); 338 } |
339 |
340 VecPredRegContainer & 341 getWritableVecPredReg(const RegId& reg) override 342 { 343 return actualTC->getWritableVecPredReg(reg); 344 } |
345 |
346 RegVal 347 readCCReg(RegIndex reg_idx) const override 348 { 349 return actualTC->readCCReg(reg_idx); 350 } |
351 352 void |
353 setIntReg(RegIndex reg_idx, RegVal val) override |
354 { 355 actualTC->setIntReg(reg_idx, val); 356 checkerTC->setIntReg(reg_idx, val); 357 } 358 359 void |
360 setFloatReg(RegIndex reg_idx, RegVal val) override |
361 { 362 actualTC->setFloatReg(reg_idx, val); 363 checkerTC->setFloatReg(reg_idx, val); 364 } 365 366 void 367 setVecReg(const RegId& reg, const VecRegContainer& val) override 368 { --- 11 unchanged lines hidden (view full) --- 380 void 381 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override 382 { 383 actualTC->setVecPredReg(reg, val); 384 checkerTC->setVecPredReg(reg, val); 385 } 386 387 void |
388 setCCReg(RegIndex reg_idx, RegVal val) override |
389 { 390 actualTC->setCCReg(reg_idx, val); 391 checkerTC->setCCReg(reg_idx, val); 392 } 393 394 /** Reads this thread's PC state. */ |
395 TheISA::PCState pcState() const override { return actualTC->pcState(); } |
396 397 /** Sets this thread's PC state. */ 398 void 399 pcState(const TheISA::PCState &val) override 400 { 401 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 402 val, checkerTC->pcState()); 403 checkerTC->pcState(val); --- 10 unchanged lines hidden (view full) --- 414 415 void 416 pcStateNoRecord(const TheISA::PCState &val) override 417 { 418 return actualTC->pcState(val); 419 } 420 421 /** Reads this thread's PC. */ |
422 Addr instAddr() const override { return actualTC->instAddr(); } |
423 424 /** Reads this thread's next PC. */ |
425 Addr nextInstAddr() const override { return actualTC->nextInstAddr(); } |
426 427 /** Reads this thread's next PC. */ |
428 MicroPC microPC() const override { return actualTC->microPC(); } |
429 |
430 RegVal 431 readMiscRegNoEffect(RegIndex misc_reg) const override 432 { 433 return actualTC->readMiscRegNoEffect(misc_reg); 434 } |
435 |
436 RegVal 437 readMiscReg(RegIndex misc_reg) override 438 { 439 return actualTC->readMiscReg(misc_reg); 440 } |
441 442 void |
443 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override |
444 { 445 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 446 " and O3..\n", misc_reg); 447 checkerTC->setMiscRegNoEffect(misc_reg, val); 448 actualTC->setMiscRegNoEffect(misc_reg, val); 449 } 450 451 void |
452 setMiscReg(RegIndex misc_reg, RegVal val) override |
453 { 454 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 455 " and O3..\n", misc_reg); 456 checkerTC->setMiscReg(misc_reg, val); 457 actualTC->setMiscReg(misc_reg, val); 458 } 459 460 RegId 461 flattenRegId(const RegId& regId) const override 462 { 463 return actualTC->flattenRegId(regId); 464 } 465 |
466 unsigned 467 readStCondFailures() const override 468 { 469 return actualTC->readStCondFailures(); 470 } |
471 472 void 473 setStCondFailures(unsigned sc_failures) override 474 { 475 actualTC->setStCondFailures(sc_failures); 476 } 477 |
478 Counter 479 readFuncExeInst() const override 480 { 481 return actualTC->readFuncExeInst(); 482 } |
483 |
484 RegVal 485 readIntRegFlat(RegIndex idx) const override 486 { |
487 return actualTC->readIntRegFlat(idx); 488 } 489 490 void |
491 setIntRegFlat(RegIndex idx, RegVal val) override |
492 { 493 actualTC->setIntRegFlat(idx, val); 494 } 495 496 RegVal |
497 readFloatRegFlat(RegIndex idx) const override |
498 { 499 return actualTC->readFloatRegFlat(idx); 500 } 501 502 void |
503 setFloatRegFlat(RegIndex idx, RegVal val) override |
504 { 505 actualTC->setFloatRegFlat(idx, val); 506 } 507 508 const VecRegContainer & |
509 readVecRegFlat(RegIndex idx) const override |
510 { 511 return actualTC->readVecRegFlat(idx); 512 } 513 514 /** 515 * Read vector register for modification, flat indexing. 516 */ 517 VecRegContainer & |
518 getWritableVecRegFlat(RegIndex idx) override |
519 { 520 return actualTC->getWritableVecRegFlat(idx); 521 } 522 |
523 void 524 setVecRegFlat(RegIndex idx, const VecRegContainer& val) override 525 { 526 actualTC->setVecRegFlat(idx, val); 527 } |
528 |
529 const VecElem & 530 readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override 531 { 532 return actualTC->readVecElemFlat(idx, elem_idx); 533 } |
534 |
535 void 536 setVecElemFlat(RegIndex idx, 537 const ElemIndex& elem_idx, const VecElem& val) override 538 { 539 actualTC->setVecElemFlat(idx, elem_idx, val); 540 } |
541 |
542 const VecPredRegContainer & 543 readVecPredRegFlat(RegIndex idx) const override 544 { 545 return actualTC->readVecPredRegFlat(idx); 546 } |
547 |
548 VecPredRegContainer & 549 getWritableVecPredRegFlat(RegIndex idx) override 550 { 551 return actualTC->getWritableVecPredRegFlat(idx); 552 } |
553 |
554 void 555 setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override 556 { 557 actualTC->setVecPredRegFlat(idx, val); 558 } |
559 |
560 RegVal 561 readCCRegFlat(RegIndex idx) const override 562 { 563 return actualTC->readCCRegFlat(idx); 564 } |
565 |
566 void 567 setCCRegFlat(RegIndex idx, RegVal val) override 568 { 569 actualTC->setCCRegFlat(idx, val); 570 } |
571}; 572 573#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ |