1a2,13
> * Copyright (c) 2011 ARM Limited
> * All rights reserved
> *
> * The license below extends only to copyright in the software and shall
> * not be construed as granting a license to any other intellectual
> * property including but not limited to intellectual property relating
> * to a hardware implementation of the functionality of the software
> * licensed hereunder. You may use the software subject to the license
> * terms below provided that you ensure that this notice is replicated
> * unmodified and in its entirety in all distributions of the software,
> * modified or unmodified, in source code or in binary form.
> *
38a51
> #include "debug/Checker.hh"
80c93,97
< void setCpuId(int id)
---
> int cpuId() { return actualTC->cpuId(); }
>
> int contextId() { return actualTC->contextId(); }
>
> void setContextId(int id)
82,83c99,100
< actualTC->setCpuId(id);
< checkerTC->setCpuId(id);
---
> actualTC->setContextId(id);
> checkerTC->setContextId(id);
86c103,109
< int cpuId() { return actualTC->cpuId(); }
---
> /** Returns this thread's ID number. */
> int threadId() { return actualTC->threadId(); }
> void setThreadId(int id)
> {
> checkerTC->setThreadId(id);
> actualTC->setThreadId(id);
> }
92c115,118
< #if FULL_SYSTEM
---
> BaseCPU *getCheckerCpuPtr() { return checkerTC->getCpuPtr(); }
>
> Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
>
94a121
> #if FULL_SYSTEM
103a131,139
>
> //XXX: How does this work now?
> void initMemProxies(ThreadContext *tc)
> { actualTC->initMemProxies(tc); }
>
> void connectMemPorts(ThreadContext *tc)
> {
> actualTC->connectMemPorts(tc);
> }
107a144,147
>
> /** Executes a syscall in SE mode. */
> void syscall(int64_t callnum)
> { return actualTC->syscall(callnum); }
123c163
< void suspend() { actualTC->suspend(); }
---
> void suspend(int delay) { actualTC->suspend(delay); }
126c166
< void halt() { actualTC->halt(); }
---
> void halt(int delay) { actualTC->halt(delay); }
138c178,182
< void regStats(const std::string &name) { actualTC->regStats(name); }
---
> void regStats(const std::string &name)
> {
> actualTC->regStats(name);
> checkerTC->regStats(name);
> }
154,155d197
< int threadId() { return actualTC->threadId(); }
<
199c241,243
< uint64_t readPC() { return actualTC->readPC(); }
---
> /** Reads this thread's PC state. */
> TheISA::PCState pcState()
> { return actualTC->pcState(); }
201c245,246
< void setPC(uint64_t val)
---
> /** Sets this thread's PC state. */
> void pcState(const TheISA::PCState &val)
203,204c248,250
< actualTC->setPC(val);
< checkerTC->setPC(val);
---
> DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
> val, checkerTC->pcState());
> checkerTC->pcState(val);
205a252
> return actualTC->pcState(val);
208,210c255
< uint64_t readNextPC() { return actualTC->readNextPC(); }
<
< void setNextPC(uint64_t val)
---
> void pcStateNoRecord(const TheISA::PCState &val)
212,214c257
< actualTC->setNextPC(val);
< checkerTC->setNextPC(val);
< checkerCPU->recordNextPCChange(val);
---
> return actualTC->pcState(val);
217c260,262
< uint64_t readNextNPC() { return actualTC->readNextNPC(); }
---
> /** Reads this thread's PC. */
> Addr instAddr()
> { return actualTC->instAddr(); }
219,224c264,266
< void setNextNPC(uint64_t val)
< {
< actualTC->setNextNPC(val);
< checkerTC->setNextNPC(val);
< checkerCPU->recordNextPCChange(val);
< }
---
> /** Reads this thread's next PC. */
> Addr nextInstAddr()
> { return actualTC->nextInstAddr(); }
225a268,271
> /** Reads this thread's next PC. */
> MicroPC microPC()
> { return actualTC->microPC(); }
>
233a280,281
> DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
> " and O3..\n", misc_reg);
239a288,289
> DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
> " and O3..\n", misc_reg);
243a294,296
> int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
> int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
>
249d301
< checkerTC->setStCondFailures(sc_failures);