101c101,102
< void setContextId(ContextID id)override
---
> void
> setContextId(ContextID id) override
109c110,111
< void setThreadId(int id) override
---
> void
> setThreadId(int id) override
119c121,122
< CheckerCPU *getCheckerCpuPtr()override
---
> CheckerCPU *
> getCheckerCpuPtr() override
126c129,131
< TheISA::Decoder *getDecoderPtr() override {
---
> TheISA::Decoder *
> getDecoderPtr() override
> {
132,133c137,141
< TheISA::Kernel::Statistics *getKernelStats()override
< { return actualTC->getKernelStats(); }
---
> TheISA::Kernel::Statistics *
> getKernelStats() override
> {
> return actualTC->getKernelStats();
> }
141,142c149,153
< FSTranslatingPortProxy &getVirtProxy() override
< { return actualTC->getVirtProxy(); }
---
> FSTranslatingPortProxy &
> getVirtProxy() override
> {
> return actualTC->getVirtProxy();
> }
144,145c155,159
< void initMemProxies(ThreadContext *tc) override
< { actualTC->initMemProxies(tc); }
---
> void
> initMemProxies(ThreadContext *tc) override
> {
> actualTC->initMemProxies(tc);
> }
147c161,162
< void connectMemPorts(ThreadContext *tc)
---
> void
> connectMemPorts(ThreadContext *tc)
152c167,169
< SETranslatingPortProxy &getMemProxy() override {
---
> SETranslatingPortProxy &
> getMemProxy() override
> {
157,158c174,178
< void syscall(int64_t callnum, Fault *fault)override
< { return actualTC->syscall(callnum, fault); }
---
> void
> syscall(int64_t callnum, Fault *fault) override
> {
> return actualTC->syscall(callnum, fault);
> }
162c182,183
< void setStatus(Status new_status) override
---
> void
> setStatus(Status new_status) override
172c193
< void suspend() override{ actualTC->suspend(); }
---
> void suspend() override { actualTC->suspend(); }
175c196
< void halt() override{ actualTC->halt(); }
---
> void halt() override { actualTC->halt(); }
177c198
< void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); }
---
> void dumpFuncProfile() override { actualTC->dumpFuncProfile(); }
179c200,201
< void takeOverFrom(ThreadContext *oldContext) override
---
> void
> takeOverFrom(ThreadContext *oldContext) override
185c207,208
< void regStats(const std::string &name) override
---
> void
> regStats(const std::string &name) override
191c214,216
< EndQuiesceEvent *getQuiesceEvent() override {
---
> EndQuiesceEvent *
> getQuiesceEvent() override
> {
195,196c220,221
< Tick readLastActivate() override{ return actualTC->readLastActivate(); }
< Tick readLastSuspend() override{ return actualTC->readLastSuspend(); }
---
> Tick readLastActivate() override { return actualTC->readLastActivate(); }
> Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
198,199c223,224
< void profileClear() override{ return actualTC->profileClear(); }
< void profileSample() override{ return actualTC->profileSample(); }
---
> void profileClear() override { return actualTC->profileClear(); }
> void profileSample() override { return actualTC->profileSample(); }
202c227,228
< void copyArchRegs(ThreadContext *tc) override
---
> void
> copyArchRegs(ThreadContext *tc) override
208c234,235
< void clearArchRegs() override
---
> void
> clearArchRegs() override
217c244,246
< RegVal readIntReg(int reg_idx) override {
---
> RegVal
> readIntReg(RegIndex reg_idx) const override
> {
222c251
< readFloatReg(int reg_idx) override
---
> readFloatReg(RegIndex reg_idx) const override
227,228c256,260
< const VecRegContainer& readVecReg (const RegId& reg) const override
< { return actualTC->readVecReg(reg); }
---
> const VecRegContainer &
> readVecReg (const RegId &reg) const override
> {
> return actualTC->readVecReg(reg);
> }
233,234c265,269
< VecRegContainer& getWritableVecReg (const RegId& reg) override
< { return actualTC->getWritableVecReg(reg); }
---
> VecRegContainer &
> getWritableVecReg (const RegId &reg) override
> {
> return actualTC->getWritableVecReg(reg);
> }
240,241c275,278
< readVec8BitLaneReg(const RegId& reg) const override
< { return actualTC->readVec8BitLaneReg(reg); }
---
> readVec8BitLaneReg(const RegId &reg) const override
> {
> return actualTC->readVec8BitLaneReg(reg);
> }
245,246c282,285
< readVec16BitLaneReg(const RegId& reg) const override
< { return actualTC->readVec16BitLaneReg(reg); }
---
> readVec16BitLaneReg(const RegId &reg) const override
> {
> return actualTC->readVec16BitLaneReg(reg);
> }
250,251c289,292
< readVec32BitLaneReg(const RegId& reg) const override
< { return actualTC->readVec32BitLaneReg(reg); }
---
> readVec32BitLaneReg(const RegId &reg) const override
> {
> return actualTC->readVec32BitLaneReg(reg);
> }
255,256c296,299
< readVec64BitLaneReg(const RegId& reg) const override
< { return actualTC->readVec64BitLaneReg(reg); }
---
> readVec64BitLaneReg(const RegId &reg) const override
> {
> return actualTC->readVec64BitLaneReg(reg);
> }
259,270c302,325
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::Byte>& val) override
< { return actualTC->setVecLane(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::TwoByte>& val) override
< { return actualTC->setVecLane(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::FourByte>& val) override
< { return actualTC->setVecLane(reg, val); }
< virtual void setVecLane(const RegId& reg,
< const LaneData<LaneSize::EightByte>& val) override
< { return actualTC->setVecLane(reg, val); }
---
> virtual void
> setVecLane(const RegId &reg,
> const LaneData<LaneSize::Byte> &val) override
> {
> return actualTC->setVecLane(reg, val);
> }
> virtual void
> setVecLane(const RegId &reg,
> const LaneData<LaneSize::TwoByte> &val) override
> {
> return actualTC->setVecLane(reg, val);
> }
> virtual void
> setVecLane(const RegId &reg,
> const LaneData<LaneSize::FourByte> &val) override
> {
> return actualTC->setVecLane(reg, val);
> }
> virtual void
> setVecLane(const RegId &reg,
> const LaneData<LaneSize::EightByte> &val) override
> {
> return actualTC->setVecLane(reg, val);
> }
273,274c328,332
< const VecElem& readVecElem(const RegId& reg) const override
< { return actualTC->readVecElem(reg); }
---
> const VecElem &
> readVecElem(const RegId& reg) const override
> {
> return actualTC->readVecElem(reg);
> }
276,277c334,338
< const VecPredRegContainer& readVecPredReg(const RegId& reg) const override
< { return actualTC->readVecPredReg(reg); }
---
> const VecPredRegContainer &
> readVecPredReg(const RegId& reg) const override
> {
> return actualTC->readVecPredReg(reg);
> }
279,280c340,344
< VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
< { return actualTC->getWritableVecPredReg(reg); }
---
> VecPredRegContainer &
> getWritableVecPredReg(const RegId& reg) override
> {
> return actualTC->getWritableVecPredReg(reg);
> }
282,283c346,350
< RegVal readCCReg(int reg_idx) override
< { return actualTC->readCCReg(reg_idx); }
---
> RegVal
> readCCReg(RegIndex reg_idx) const override
> {
> return actualTC->readCCReg(reg_idx);
> }
286c353
< setIntReg(int reg_idx, RegVal val) override
---
> setIntReg(RegIndex reg_idx, RegVal val) override
293c360
< setFloatReg(int reg_idx, RegVal val) override
---
> setFloatReg(RegIndex reg_idx, RegVal val) override
321c388
< setCCReg(int reg_idx, RegVal val) override
---
> setCCReg(RegIndex reg_idx, RegVal val) override
328,329c395
< TheISA::PCState pcState() override
< { return actualTC->pcState(); }
---
> TheISA::PCState pcState() const override { return actualTC->pcState(); }
356,357c422
< Addr instAddr() override
< { return actualTC->instAddr(); }
---
> Addr instAddr() const override { return actualTC->instAddr(); }
360,361c425
< Addr nextInstAddr() override
< { return actualTC->nextInstAddr(); }
---
> Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
364,365c428
< MicroPC microPC() override
< { return actualTC->microPC(); }
---
> MicroPC microPC() const override { return actualTC->microPC(); }
367,368c430,434
< RegVal readMiscRegNoEffect(int misc_reg) const override
< { return actualTC->readMiscRegNoEffect(misc_reg); }
---
> RegVal
> readMiscRegNoEffect(RegIndex misc_reg) const override
> {
> return actualTC->readMiscRegNoEffect(misc_reg);
> }
370,371c436,440
< RegVal readMiscReg(int misc_reg) override
< { return actualTC->readMiscReg(misc_reg); }
---
> RegVal
> readMiscReg(RegIndex misc_reg) override
> {
> return actualTC->readMiscReg(misc_reg);
> }
374c443
< setMiscRegNoEffect(int misc_reg, RegVal val) override
---
> setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
383c452
< setMiscReg(int misc_reg, RegVal val) override
---
> setMiscReg(RegIndex misc_reg, RegVal val) override
397,398c466,470
< unsigned readStCondFailures() override
< { return actualTC->readStCondFailures(); }
---
> unsigned
> readStCondFailures() const override
> {
> return actualTC->readStCondFailures();
> }
406c478,482
< Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
---
> Counter
> readFuncExeInst() const override
> {
> return actualTC->readFuncExeInst();
> }
408c484,486
< RegVal readIntRegFlat(int idx) override {
---
> RegVal
> readIntRegFlat(RegIndex idx) const override
> {
413c491
< setIntRegFlat(int idx, RegVal val) override
---
> setIntRegFlat(RegIndex idx, RegVal val) override
419c497
< readFloatRegFlat(int idx) override
---
> readFloatRegFlat(RegIndex idx) const override
425c503
< setFloatRegFlat(int idx, RegVal val) override
---
> setFloatRegFlat(RegIndex idx, RegVal val) override
431c509
< readVecRegFlat(int idx) const override
---
> readVecRegFlat(RegIndex idx) const override
440c518
< getWritableVecRegFlat(int idx) override
---
> getWritableVecRegFlat(RegIndex idx) override
445,446c523,527
< void setVecRegFlat(int idx, const VecRegContainer& val) override
< { actualTC->setVecRegFlat(idx, val); }
---
> void
> setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
> {
> actualTC->setVecRegFlat(idx, val);
> }
448,450c529,533
< const VecElem& readVecElemFlat(const RegIndex& idx,
< const ElemIndex& elem_idx) const override
< { return actualTC->readVecElemFlat(idx, elem_idx); }
---
> const VecElem &
> readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
> {
> return actualTC->readVecElemFlat(idx, elem_idx);
> }
452,454c535,540
< void setVecElemFlat(const RegIndex& idx,
< const ElemIndex& elem_idx, const VecElem& val) override
< { actualTC->setVecElemFlat(idx, elem_idx, val); }
---
> void
> setVecElemFlat(RegIndex idx,
> const ElemIndex& elem_idx, const VecElem& val) override
> {
> actualTC->setVecElemFlat(idx, elem_idx, val);
> }
456,457c542,546
< const VecPredRegContainer& readVecPredRegFlat(int idx) const override
< { return actualTC->readVecPredRegFlat(idx); }
---
> const VecPredRegContainer &
> readVecPredRegFlat(RegIndex idx) const override
> {
> return actualTC->readVecPredRegFlat(idx);
> }
459,460c548,552
< VecPredRegContainer& getWritableVecPredRegFlat(int idx) override
< { return actualTC->getWritableVecPredRegFlat(idx); }
---
> VecPredRegContainer &
> getWritableVecPredRegFlat(RegIndex idx) override
> {
> return actualTC->getWritableVecPredRegFlat(idx);
> }
462,463c554,558
< void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
< { actualTC->setVecPredRegFlat(idx, val); }
---
> void
> setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
> {
> actualTC->setVecPredRegFlat(idx, val);
> }
465,466c560,564
< RegVal readCCRegFlat(int idx) override
< { return actualTC->readCCRegFlat(idx); }
---
> RegVal
> readCCRegFlat(RegIndex idx) const override
> {
> return actualTC->readCCRegFlat(idx);
> }
468,469c566,570
< void setCCRegFlat(int idx, RegVal val) override
< { actualTC->setCCRegFlat(idx, val); }
---
> void
> setCCRegFlat(RegIndex idx, RegVal val) override
> {
> actualTC->setCCRegFlat(idx, val);
> }