93c93
< BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
---
> BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
95c95
< uint32_t socketId() const { return actualTC->socketId(); }
---
> uint32_t socketId() const override { return actualTC->socketId(); }
97c97
< int cpuId() const { return actualTC->cpuId(); }
---
> int cpuId() const override { return actualTC->cpuId(); }
99c99
< ContextID contextId() const { return actualTC->contextId(); }
---
> ContextID contextId() const override { return actualTC->contextId(); }
101c101
< void setContextId(ContextID id)
---
> void setContextId(ContextID id)override
108,109c108,109
< int threadId() const { return actualTC->threadId(); }
< void setThreadId(int id)
---
> int threadId() const override { return actualTC->threadId(); }
> void setThreadId(int id) override
115c115
< BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
---
> BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
117c117
< BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
---
> BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
119c119
< CheckerCPU *getCheckerCpuPtr()
---
> CheckerCPU *getCheckerCpuPtr()override
124c124,126
< TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
---
> TheISA::Decoder *getDecoderPtr() override {
> return actualTC->getDecoderPtr();
> }
126c128
< System *getSystemPtr() { return actualTC->getSystemPtr(); }
---
> System *getSystemPtr() override { return actualTC->getSystemPtr(); }
128c130
< TheISA::Kernel::Statistics *getKernelStats()
---
> TheISA::Kernel::Statistics *getKernelStats()override
131c133
< Process *getProcessPtr() { return actualTC->getProcessPtr(); }
---
> Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
133c135
< void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
---
> void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
135c137
< PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
---
> PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
137c139
< FSTranslatingPortProxy &getVirtProxy()
---
> FSTranslatingPortProxy &getVirtProxy() override
140c142
< void initMemProxies(ThreadContext *tc)
---
> void initMemProxies(ThreadContext *tc) override
148c150,152
< SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
---
> SETranslatingPortProxy &getMemProxy() override {
> return actualTC->getMemProxy();
> }
151c155
< void syscall(int64_t callnum, Fault *fault)
---
> void syscall(int64_t callnum, Fault *fault)override
154c158
< Status status() const { return actualTC->status(); }
---
> Status status() const override { return actualTC->status(); }
156c160
< void setStatus(Status new_status)
---
> void setStatus(Status new_status) override
163c167
< void activate() { actualTC->activate(); }
---
> void activate() override { actualTC->activate(); }
166c170
< void suspend() { actualTC->suspend(); }
---
> void suspend() override{ actualTC->suspend(); }
169c173
< void halt() { actualTC->halt(); }
---
> void halt() override{ actualTC->halt(); }
171c175
< void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
---
> void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); }
173c177
< void takeOverFrom(ThreadContext *oldContext)
---
> void takeOverFrom(ThreadContext *oldContext) override
179c183
< void regStats(const std::string &name)
---
> void regStats(const std::string &name) override
185c189,191
< EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
---
> EndQuiesceEvent *getQuiesceEvent() override {
> return actualTC->getQuiesceEvent();
> }
187,188c193,194
< Tick readLastActivate() { return actualTC->readLastActivate(); }
< Tick readLastSuspend() { return actualTC->readLastSuspend(); }
---
> Tick readLastActivate() override{ return actualTC->readLastActivate(); }
> Tick readLastSuspend() override{ return actualTC->readLastSuspend(); }
190,191c196,197
< void profileClear() { return actualTC->profileClear(); }
< void profileSample() { return actualTC->profileSample(); }
---
> void profileClear() override{ return actualTC->profileClear(); }
> void profileSample() override{ return actualTC->profileSample(); }
194c200
< void copyArchRegs(ThreadContext *tc)
---
> void copyArchRegs(ThreadContext *tc) override
200c206
< void clearArchRegs()
---
> void clearArchRegs() override
209c215,217
< RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
---
> RegVal readIntReg(int reg_idx) override {
> return actualTC->readIntReg(reg_idx);
> }
212c220
< readFloatReg(int reg_idx)
---
> readFloatReg(int reg_idx) override
217c225
< const VecRegContainer& readVecReg(const RegId& reg) const
---
> const VecRegContainer& readVecReg (const RegId& reg) const override
223c231
< VecRegContainer& getWritableVecReg(const RegId& reg)
---
> VecRegContainer& getWritableVecReg (const RegId& reg) override
230c238
< readVec8BitLaneReg(const RegId& reg) const
---
> readVec8BitLaneReg(const RegId& reg) const override
235c243
< readVec16BitLaneReg(const RegId& reg) const
---
> readVec16BitLaneReg(const RegId& reg) const override
240c248
< readVec32BitLaneReg(const RegId& reg) const
---
> readVec32BitLaneReg(const RegId& reg) const override
245c253
< readVec64BitLaneReg(const RegId& reg) const
---
> readVec64BitLaneReg(const RegId& reg) const override
250c258
< const LaneData<LaneSize::Byte>& val)
---
> const LaneData<LaneSize::Byte>& val) override
253c261
< const LaneData<LaneSize::TwoByte>& val)
---
> const LaneData<LaneSize::TwoByte>& val) override
256c264
< const LaneData<LaneSize::FourByte>& val)
---
> const LaneData<LaneSize::FourByte>& val) override
259c267
< const LaneData<LaneSize::EightByte>& val)
---
> const LaneData<LaneSize::EightByte>& val) override
263c271
< const VecElem& readVecElem(const RegId& reg) const
---
> const VecElem& readVecElem(const RegId& reg) const override
272c280
< RegVal readCCReg(int reg_idx)
---
> RegVal readCCReg(int reg_idx) override
276c284
< setIntReg(int reg_idx, RegVal val)
---
> setIntReg(int reg_idx, RegVal val) override
283c291
< setFloatReg(int reg_idx, RegVal val)
---
> setFloatReg(int reg_idx, RegVal val) override
290c298
< setVecReg(const RegId& reg, const VecRegContainer& val)
---
> setVecReg(const RegId& reg, const VecRegContainer& val) override
297c305
< setVecElem(const RegId& reg, const VecElem& val)
---
> setVecElem(const RegId& reg, const VecElem& val) override
304c312
< setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
---
> setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
311c319
< setCCReg(int reg_idx, RegVal val)
---
> setCCReg(int reg_idx, RegVal val) override
318c326
< TheISA::PCState pcState()
---
> TheISA::PCState pcState() override
323c331
< pcState(const TheISA::PCState &val)
---
> pcState(const TheISA::PCState &val) override
340c348
< pcStateNoRecord(const TheISA::PCState &val)
---
> pcStateNoRecord(const TheISA::PCState &val) override
346c354
< Addr instAddr()
---
> Addr instAddr() override
350c358
< Addr nextInstAddr()
---
> Addr nextInstAddr() override
354c362
< MicroPC microPC()
---
> MicroPC microPC() override
357c365
< RegVal readMiscRegNoEffect(int misc_reg) const
---
> RegVal readMiscRegNoEffect(int misc_reg) const override
360c368
< RegVal readMiscReg(int misc_reg)
---
> RegVal readMiscReg(int misc_reg) override
364c372
< setMiscRegNoEffect(int misc_reg, RegVal val)
---
> setMiscRegNoEffect(int misc_reg, RegVal val) override
373c381
< setMiscReg(int misc_reg, RegVal val)
---
> setMiscReg(int misc_reg, RegVal val) override
382c390
< flattenRegId(const RegId& regId) const
---
> flattenRegId(const RegId& regId) const override
387c395
< unsigned readStCondFailures()
---
> unsigned readStCondFailures() override
391c399
< setStCondFailures(unsigned sc_failures)
---
> setStCondFailures(unsigned sc_failures) override
396c404
< Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
---
> Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
398c406,408
< RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
---
> RegVal readIntRegFlat(int idx) override {
> return actualTC->readIntRegFlat(idx);
> }
401c411
< setIntRegFlat(int idx, RegVal val)
---
> setIntRegFlat(int idx, RegVal val) override
407c417
< readFloatRegFlat(int idx)
---
> readFloatRegFlat(int idx) override
413c423
< setFloatRegFlat(int idx, RegVal val)
---
> setFloatRegFlat(int idx, RegVal val) override
419c429
< readVecRegFlat(int idx) const
---
> readVecRegFlat(int idx) const override
428c438
< getWritableVecRegFlat(int idx)
---
> getWritableVecRegFlat(int idx) override
433c443
< void setVecRegFlat(int idx, const VecRegContainer& val)
---
> void setVecRegFlat(int idx, const VecRegContainer& val) override
437c447
< const ElemIndex& elem_idx) const
---
> const ElemIndex& elem_idx) const override
441c451
< const ElemIndex& elem_idx, const VecElem& val)
---
> const ElemIndex& elem_idx, const VecElem& val) override
453c463
< RegVal readCCRegFlat(int idx)
---
> RegVal readCCRegFlat(int idx) override
456c466
< void setCCRegFlat(int idx, RegVal val)
---
> void setCCRegFlat(int idx, RegVal val) override
< BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
---
> BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
95c95
< uint32_t socketId() const { return actualTC->socketId(); }
---
> uint32_t socketId() const override { return actualTC->socketId(); }
97c97
< int cpuId() const { return actualTC->cpuId(); }
---
> int cpuId() const override { return actualTC->cpuId(); }
99c99
< ContextID contextId() const { return actualTC->contextId(); }
---
> ContextID contextId() const override { return actualTC->contextId(); }
101c101
< void setContextId(ContextID id)
---
> void setContextId(ContextID id)override
108,109c108,109
< int threadId() const { return actualTC->threadId(); }
< void setThreadId(int id)
---
> int threadId() const override { return actualTC->threadId(); }
> void setThreadId(int id) override
115c115
< BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
---
> BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
117c117
< BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
---
> BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
119c119
< CheckerCPU *getCheckerCpuPtr()
---
> CheckerCPU *getCheckerCpuPtr()override
124c124,126
< TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
---
> TheISA::Decoder *getDecoderPtr() override {
> return actualTC->getDecoderPtr();
> }
126c128
< System *getSystemPtr() { return actualTC->getSystemPtr(); }
---
> System *getSystemPtr() override { return actualTC->getSystemPtr(); }
128c130
< TheISA::Kernel::Statistics *getKernelStats()
---
> TheISA::Kernel::Statistics *getKernelStats()override
131c133
< Process *getProcessPtr() { return actualTC->getProcessPtr(); }
---
> Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
133c135
< void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
---
> void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
135c137
< PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
---
> PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
137c139
< FSTranslatingPortProxy &getVirtProxy()
---
> FSTranslatingPortProxy &getVirtProxy() override
140c142
< void initMemProxies(ThreadContext *tc)
---
> void initMemProxies(ThreadContext *tc) override
148c150,152
< SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
---
> SETranslatingPortProxy &getMemProxy() override {
> return actualTC->getMemProxy();
> }
151c155
< void syscall(int64_t callnum, Fault *fault)
---
> void syscall(int64_t callnum, Fault *fault)override
154c158
< Status status() const { return actualTC->status(); }
---
> Status status() const override { return actualTC->status(); }
156c160
< void setStatus(Status new_status)
---
> void setStatus(Status new_status) override
163c167
< void activate() { actualTC->activate(); }
---
> void activate() override { actualTC->activate(); }
166c170
< void suspend() { actualTC->suspend(); }
---
> void suspend() override{ actualTC->suspend(); }
169c173
< void halt() { actualTC->halt(); }
---
> void halt() override{ actualTC->halt(); }
171c175
< void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
---
> void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); }
173c177
< void takeOverFrom(ThreadContext *oldContext)
---
> void takeOverFrom(ThreadContext *oldContext) override
179c183
< void regStats(const std::string &name)
---
> void regStats(const std::string &name) override
185c189,191
< EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
---
> EndQuiesceEvent *getQuiesceEvent() override {
> return actualTC->getQuiesceEvent();
> }
187,188c193,194
< Tick readLastActivate() { return actualTC->readLastActivate(); }
< Tick readLastSuspend() { return actualTC->readLastSuspend(); }
---
> Tick readLastActivate() override{ return actualTC->readLastActivate(); }
> Tick readLastSuspend() override{ return actualTC->readLastSuspend(); }
190,191c196,197
< void profileClear() { return actualTC->profileClear(); }
< void profileSample() { return actualTC->profileSample(); }
---
> void profileClear() override{ return actualTC->profileClear(); }
> void profileSample() override{ return actualTC->profileSample(); }
194c200
< void copyArchRegs(ThreadContext *tc)
---
> void copyArchRegs(ThreadContext *tc) override
200c206
< void clearArchRegs()
---
> void clearArchRegs() override
209c215,217
< RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
---
> RegVal readIntReg(int reg_idx) override {
> return actualTC->readIntReg(reg_idx);
> }
212c220
< readFloatReg(int reg_idx)
---
> readFloatReg(int reg_idx) override
217c225
< const VecRegContainer& readVecReg(const RegId& reg) const
---
> const VecRegContainer& readVecReg (const RegId& reg) const override
223c231
< VecRegContainer& getWritableVecReg(const RegId& reg)
---
> VecRegContainer& getWritableVecReg (const RegId& reg) override
230c238
< readVec8BitLaneReg(const RegId& reg) const
---
> readVec8BitLaneReg(const RegId& reg) const override
235c243
< readVec16BitLaneReg(const RegId& reg) const
---
> readVec16BitLaneReg(const RegId& reg) const override
240c248
< readVec32BitLaneReg(const RegId& reg) const
---
> readVec32BitLaneReg(const RegId& reg) const override
245c253
< readVec64BitLaneReg(const RegId& reg) const
---
> readVec64BitLaneReg(const RegId& reg) const override
250c258
< const LaneData<LaneSize::Byte>& val)
---
> const LaneData<LaneSize::Byte>& val) override
253c261
< const LaneData<LaneSize::TwoByte>& val)
---
> const LaneData<LaneSize::TwoByte>& val) override
256c264
< const LaneData<LaneSize::FourByte>& val)
---
> const LaneData<LaneSize::FourByte>& val) override
259c267
< const LaneData<LaneSize::EightByte>& val)
---
> const LaneData<LaneSize::EightByte>& val) override
263c271
< const VecElem& readVecElem(const RegId& reg) const
---
> const VecElem& readVecElem(const RegId& reg) const override
272c280
< RegVal readCCReg(int reg_idx)
---
> RegVal readCCReg(int reg_idx) override
276c284
< setIntReg(int reg_idx, RegVal val)
---
> setIntReg(int reg_idx, RegVal val) override
283c291
< setFloatReg(int reg_idx, RegVal val)
---
> setFloatReg(int reg_idx, RegVal val) override
290c298
< setVecReg(const RegId& reg, const VecRegContainer& val)
---
> setVecReg(const RegId& reg, const VecRegContainer& val) override
297c305
< setVecElem(const RegId& reg, const VecElem& val)
---
> setVecElem(const RegId& reg, const VecElem& val) override
304c312
< setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
---
> setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
311c319
< setCCReg(int reg_idx, RegVal val)
---
> setCCReg(int reg_idx, RegVal val) override
318c326
< TheISA::PCState pcState()
---
> TheISA::PCState pcState() override
323c331
< pcState(const TheISA::PCState &val)
---
> pcState(const TheISA::PCState &val) override
340c348
< pcStateNoRecord(const TheISA::PCState &val)
---
> pcStateNoRecord(const TheISA::PCState &val) override
346c354
< Addr instAddr()
---
> Addr instAddr() override
350c358
< Addr nextInstAddr()
---
> Addr nextInstAddr() override
354c362
< MicroPC microPC()
---
> MicroPC microPC() override
357c365
< RegVal readMiscRegNoEffect(int misc_reg) const
---
> RegVal readMiscRegNoEffect(int misc_reg) const override
360c368
< RegVal readMiscReg(int misc_reg)
---
> RegVal readMiscReg(int misc_reg) override
364c372
< setMiscRegNoEffect(int misc_reg, RegVal val)
---
> setMiscRegNoEffect(int misc_reg, RegVal val) override
373c381
< setMiscReg(int misc_reg, RegVal val)
---
> setMiscReg(int misc_reg, RegVal val) override
382c390
< flattenRegId(const RegId& regId) const
---
> flattenRegId(const RegId& regId) const override
387c395
< unsigned readStCondFailures()
---
> unsigned readStCondFailures() override
391c399
< setStCondFailures(unsigned sc_failures)
---
> setStCondFailures(unsigned sc_failures) override
396c404
< Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
---
> Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
398c406,408
< RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
---
> RegVal readIntRegFlat(int idx) override {
> return actualTC->readIntRegFlat(idx);
> }
401c411
< setIntRegFlat(int idx, RegVal val)
---
> setIntRegFlat(int idx, RegVal val) override
407c417
< readFloatRegFlat(int idx)
---
> readFloatRegFlat(int idx) override
413c423
< setFloatRegFlat(int idx, RegVal val)
---
> setFloatRegFlat(int idx, RegVal val) override
419c429
< readVecRegFlat(int idx) const
---
> readVecRegFlat(int idx) const override
428c438
< getWritableVecRegFlat(int idx)
---
> getWritableVecRegFlat(int idx) override
433c443
< void setVecRegFlat(int idx, const VecRegContainer& val)
---
> void setVecRegFlat(int idx, const VecRegContainer& val) override
437c447
< const ElemIndex& elem_idx) const
---
> const ElemIndex& elem_idx) const override
441c451
< const ElemIndex& elem_idx, const VecElem& val)
---
> const ElemIndex& elem_idx, const VecElem& val) override
453c463
< RegVal readCCRegFlat(int idx)
---
> RegVal readCCRegFlat(int idx) override
456c466
< void setCCRegFlat(int idx, RegVal val)
---
> void setCCRegFlat(int idx, RegVal val) override