1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
32#define __CPU_CHECKER_THREAD_CONTEXT_HH__
33
34#include "arch/types.hh"
35#include "config/the_isa.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/simple_thread.hh"
38#include "cpu/thread_context.hh"
39
40class EndQuiesceEvent;
41namespace TheISA {
42 namespace Kernel {
43 class Statistics;
44 };
45};
46
47/**
48 * Derived ThreadContext class for use with the Checker. The template
49 * parameter is the ThreadContext class used by the specific CPU being
50 * verified. This CheckerThreadContext is then used by the main CPU
51 * in place of its usual ThreadContext class. It handles updating the
52 * checker's state any time state is updated externally through the
53 * ThreadContext.
54 */
55template <class TC>
56class CheckerThreadContext : public ThreadContext
57{
58 public:
59 CheckerThreadContext(TC *actual_tc,
60 CheckerCPU *checker_cpu)
61 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
62 checkerCPU(checker_cpu)
63 { }
64
65 private:
66 /** The main CPU's ThreadContext, or class that implements the
67 * ThreadContext interface. */
68 TC *actualTC;
69 /** The checker's own SimpleThread. Will be updated any time
70 * anything uses this ThreadContext to externally update a
71 * thread's state. */
72 SimpleThread *checkerTC;
73 /** Pointer to the checker CPU. */
74 CheckerCPU *checkerCPU;
75
76 public:
77
78 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
79
80 void setCpuId(int id)
81 {
82 actualTC->setCpuId(id);
83 checkerTC->setCpuId(id);
84 }
85
86 int cpuId() { return actualTC->cpuId(); }
87
88 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
89
90 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
91
92#if FULL_SYSTEM
93 System *getSystemPtr() { return actualTC->getSystemPtr(); }
94
95 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
96
97 TheISA::Kernel::Statistics *getKernelStats()
98 { return actualTC->getKernelStats(); }
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
32#define __CPU_CHECKER_THREAD_CONTEXT_HH__
33
34#include "arch/types.hh"
35#include "config/the_isa.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/simple_thread.hh"
38#include "cpu/thread_context.hh"
39
40class EndQuiesceEvent;
41namespace TheISA {
42 namespace Kernel {
43 class Statistics;
44 };
45};
46
47/**
48 * Derived ThreadContext class for use with the Checker. The template
49 * parameter is the ThreadContext class used by the specific CPU being
50 * verified. This CheckerThreadContext is then used by the main CPU
51 * in place of its usual ThreadContext class. It handles updating the
52 * checker's state any time state is updated externally through the
53 * ThreadContext.
54 */
55template <class TC>
56class CheckerThreadContext : public ThreadContext
57{
58 public:
59 CheckerThreadContext(TC *actual_tc,
60 CheckerCPU *checker_cpu)
61 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
62 checkerCPU(checker_cpu)
63 { }
64
65 private:
66 /** The main CPU's ThreadContext, or class that implements the
67 * ThreadContext interface. */
68 TC *actualTC;
69 /** The checker's own SimpleThread. Will be updated any time
70 * anything uses this ThreadContext to externally update a
71 * thread's state. */
72 SimpleThread *checkerTC;
73 /** Pointer to the checker CPU. */
74 CheckerCPU *checkerCPU;
75
76 public:
77
78 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
79
80 void setCpuId(int id)
81 {
82 actualTC->setCpuId(id);
83 checkerTC->setCpuId(id);
84 }
85
86 int cpuId() { return actualTC->cpuId(); }
87
88 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
89
90 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
91
92#if FULL_SYSTEM
93 System *getSystemPtr() { return actualTC->getSystemPtr(); }
94
95 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
96
97 TheISA::Kernel::Statistics *getKernelStats()
98 { return actualTC->getKernelStats(); }
|
102
103 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
104
105 VirtualPort *getVirtPort()
106 { return actualTC->getVirtPort(); }
107
108 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
109
110 Status status() const { return actualTC->status(); }
111
112 void setStatus(Status new_status)
113 {
114 actualTC->setStatus(new_status);
115 checkerTC->setStatus(new_status);
116 }
117
118 /// Set the status to Active. Optional delay indicates number of
119 /// cycles to wait before beginning execution.
120 void activate(int delay = 1) { actualTC->activate(delay); }
121
122 /// Set the status to Suspended.
123 void suspend() { actualTC->suspend(); }
124
125 /// Set the status to Halted.
126 void halt() { actualTC->halt(); }
127
128#if FULL_SYSTEM
129 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
130#endif
131
132 void takeOverFrom(ThreadContext *oldContext)
133 {
134 actualTC->takeOverFrom(oldContext);
135 checkerTC->copyState(oldContext);
136 }
137
138 void regStats(const std::string &name) { actualTC->regStats(name); }
139
140 void serialize(std::ostream &os) { actualTC->serialize(os); }
141 void unserialize(Checkpoint *cp, const std::string §ion)
142 { actualTC->unserialize(cp, section); }
143
144#if FULL_SYSTEM
145 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
146
147 Tick readLastActivate() { return actualTC->readLastActivate(); }
148 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
149
150 void profileClear() { return actualTC->profileClear(); }
151 void profileSample() { return actualTC->profileSample(); }
152#endif
153
154 int threadId() { return actualTC->threadId(); }
155
156 // @todo: Do I need this?
157 void copyArchRegs(ThreadContext *tc)
158 {
159 actualTC->copyArchRegs(tc);
160 checkerTC->copyArchRegs(tc);
161 }
162
163 void clearArchRegs()
164 {
165 actualTC->clearArchRegs();
166 checkerTC->clearArchRegs();
167 }
168
169 //
170 // New accessors for new decoder.
171 //
172 uint64_t readIntReg(int reg_idx)
173 { return actualTC->readIntReg(reg_idx); }
174
175 FloatReg readFloatReg(int reg_idx)
176 { return actualTC->readFloatReg(reg_idx); }
177
178 FloatRegBits readFloatRegBits(int reg_idx)
179 { return actualTC->readFloatRegBits(reg_idx); }
180
181 void setIntReg(int reg_idx, uint64_t val)
182 {
183 actualTC->setIntReg(reg_idx, val);
184 checkerTC->setIntReg(reg_idx, val);
185 }
186
187 void setFloatReg(int reg_idx, FloatReg val)
188 {
189 actualTC->setFloatReg(reg_idx, val);
190 checkerTC->setFloatReg(reg_idx, val);
191 }
192
193 void setFloatRegBits(int reg_idx, FloatRegBits val)
194 {
195 actualTC->setFloatRegBits(reg_idx, val);
196 checkerTC->setFloatRegBits(reg_idx, val);
197 }
198
199 uint64_t readPC() { return actualTC->readPC(); }
200
201 void setPC(uint64_t val)
202 {
203 actualTC->setPC(val);
204 checkerTC->setPC(val);
205 checkerCPU->recordPCChange(val);
206 }
207
208 uint64_t readNextPC() { return actualTC->readNextPC(); }
209
210 void setNextPC(uint64_t val)
211 {
212 actualTC->setNextPC(val);
213 checkerTC->setNextPC(val);
214 checkerCPU->recordNextPCChange(val);
215 }
216
217 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
218
219 void setNextNPC(uint64_t val)
220 {
221 actualTC->setNextNPC(val);
222 checkerTC->setNextNPC(val);
223 checkerCPU->recordNextPCChange(val);
224 }
225
226 MiscReg readMiscRegNoEffect(int misc_reg)
227 { return actualTC->readMiscRegNoEffect(misc_reg); }
228
229 MiscReg readMiscReg(int misc_reg)
230 { return actualTC->readMiscReg(misc_reg); }
231
232 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
233 {
234 checkerTC->setMiscRegNoEffect(misc_reg, val);
235 actualTC->setMiscRegNoEffect(misc_reg, val);
236 }
237
238 void setMiscReg(int misc_reg, const MiscReg &val)
239 {
240 checkerTC->setMiscReg(misc_reg, val);
241 actualTC->setMiscReg(misc_reg, val);
242 }
243
244 unsigned readStCondFailures()
245 { return actualTC->readStCondFailures(); }
246
247 void setStCondFailures(unsigned sc_failures)
248 {
249 checkerTC->setStCondFailures(sc_failures);
250 actualTC->setStCondFailures(sc_failures);
251 }
252
253 // @todo: Fix this!
254 bool misspeculating() { return actualTC->misspeculating(); }
255
256#if !FULL_SYSTEM
257 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
258#endif
259};
260
261#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
| 101
102 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
103
104 VirtualPort *getVirtPort()
105 { return actualTC->getVirtPort(); }
106
107 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
108
109 Status status() const { return actualTC->status(); }
110
111 void setStatus(Status new_status)
112 {
113 actualTC->setStatus(new_status);
114 checkerTC->setStatus(new_status);
115 }
116
117 /// Set the status to Active. Optional delay indicates number of
118 /// cycles to wait before beginning execution.
119 void activate(int delay = 1) { actualTC->activate(delay); }
120
121 /// Set the status to Suspended.
122 void suspend() { actualTC->suspend(); }
123
124 /// Set the status to Halted.
125 void halt() { actualTC->halt(); }
126
127#if FULL_SYSTEM
128 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
129#endif
130
131 void takeOverFrom(ThreadContext *oldContext)
132 {
133 actualTC->takeOverFrom(oldContext);
134 checkerTC->copyState(oldContext);
135 }
136
137 void regStats(const std::string &name) { actualTC->regStats(name); }
138
139 void serialize(std::ostream &os) { actualTC->serialize(os); }
140 void unserialize(Checkpoint *cp, const std::string §ion)
141 { actualTC->unserialize(cp, section); }
142
143#if FULL_SYSTEM
144 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
145
146 Tick readLastActivate() { return actualTC->readLastActivate(); }
147 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
148
149 void profileClear() { return actualTC->profileClear(); }
150 void profileSample() { return actualTC->profileSample(); }
151#endif
152
153 int threadId() { return actualTC->threadId(); }
154
155 // @todo: Do I need this?
156 void copyArchRegs(ThreadContext *tc)
157 {
158 actualTC->copyArchRegs(tc);
159 checkerTC->copyArchRegs(tc);
160 }
161
162 void clearArchRegs()
163 {
164 actualTC->clearArchRegs();
165 checkerTC->clearArchRegs();
166 }
167
168 //
169 // New accessors for new decoder.
170 //
171 uint64_t readIntReg(int reg_idx)
172 { return actualTC->readIntReg(reg_idx); }
173
174 FloatReg readFloatReg(int reg_idx)
175 { return actualTC->readFloatReg(reg_idx); }
176
177 FloatRegBits readFloatRegBits(int reg_idx)
178 { return actualTC->readFloatRegBits(reg_idx); }
179
180 void setIntReg(int reg_idx, uint64_t val)
181 {
182 actualTC->setIntReg(reg_idx, val);
183 checkerTC->setIntReg(reg_idx, val);
184 }
185
186 void setFloatReg(int reg_idx, FloatReg val)
187 {
188 actualTC->setFloatReg(reg_idx, val);
189 checkerTC->setFloatReg(reg_idx, val);
190 }
191
192 void setFloatRegBits(int reg_idx, FloatRegBits val)
193 {
194 actualTC->setFloatRegBits(reg_idx, val);
195 checkerTC->setFloatRegBits(reg_idx, val);
196 }
197
198 uint64_t readPC() { return actualTC->readPC(); }
199
200 void setPC(uint64_t val)
201 {
202 actualTC->setPC(val);
203 checkerTC->setPC(val);
204 checkerCPU->recordPCChange(val);
205 }
206
207 uint64_t readNextPC() { return actualTC->readNextPC(); }
208
209 void setNextPC(uint64_t val)
210 {
211 actualTC->setNextPC(val);
212 checkerTC->setNextPC(val);
213 checkerCPU->recordNextPCChange(val);
214 }
215
216 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
217
218 void setNextNPC(uint64_t val)
219 {
220 actualTC->setNextNPC(val);
221 checkerTC->setNextNPC(val);
222 checkerCPU->recordNextPCChange(val);
223 }
224
225 MiscReg readMiscRegNoEffect(int misc_reg)
226 { return actualTC->readMiscRegNoEffect(misc_reg); }
227
228 MiscReg readMiscReg(int misc_reg)
229 { return actualTC->readMiscReg(misc_reg); }
230
231 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
232 {
233 checkerTC->setMiscRegNoEffect(misc_reg, val);
234 actualTC->setMiscRegNoEffect(misc_reg, val);
235 }
236
237 void setMiscReg(int misc_reg, const MiscReg &val)
238 {
239 checkerTC->setMiscReg(misc_reg, val);
240 actualTC->setMiscReg(misc_reg, val);
241 }
242
243 unsigned readStCondFailures()
244 { return actualTC->readStCondFailures(); }
245
246 void setStCondFailures(unsigned sc_failures)
247 {
248 checkerTC->setStCondFailures(sc_failures);
249 actualTC->setStCondFailures(sc_failures);
250 }
251
252 // @todo: Fix this!
253 bool misspeculating() { return actualTC->misspeculating(); }
254
255#if !FULL_SYSTEM
256 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
257#endif
258};
259
260#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
|