1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
32#define __CPU_CHECKER_THREAD_CONTEXT_HH__
33
34#include "arch/types.hh"
35#include "cpu/checker/cpu.hh"
36#include "cpu/simple_thread.hh"
37#include "cpu/thread_context.hh"
38
39class EndQuiesceEvent;
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
32#define __CPU_CHECKER_THREAD_CONTEXT_HH__
33
34#include "arch/types.hh"
35#include "cpu/checker/cpu.hh"
36#include "cpu/simple_thread.hh"
37#include "cpu/thread_context.hh"
38
39class EndQuiesceEvent;
|
42};
43
44/**
45 * Derived ThreadContext class for use with the Checker. The template
46 * parameter is the ThreadContext class used by the specific CPU being
47 * verified. This CheckerThreadContext is then used by the main CPU
48 * in place of its usual ThreadContext class. It handles updating the
49 * checker's state any time state is updated externally through the
50 * ThreadContext.
51 */
52template <class TC>
53class CheckerThreadContext : public ThreadContext
54{
55 public:
56 CheckerThreadContext(TC *actual_tc,
57 CheckerCPU *checker_cpu)
58 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
59 checkerCPU(checker_cpu)
60 { }
61
62 private:
63 /** The main CPU's ThreadContext, or class that implements the
64 * ThreadContext interface. */
65 TC *actualTC;
66 /** The checker's own SimpleThread. Will be updated any time
67 * anything uses this ThreadContext to externally update a
68 * thread's state. */
69 SimpleThread *checkerTC;
70 /** Pointer to the checker CPU. */
71 CheckerCPU *checkerCPU;
72
73 public:
74
75 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
76
77 void setCpuId(int id)
78 {
79 actualTC->setCpuId(id);
80 checkerTC->setCpuId(id);
81 }
82
83 int readCpuId() { return actualTC->readCpuId(); }
84
85#if FULL_SYSTEM
86 System *getSystemPtr() { return actualTC->getSystemPtr(); }
87
88 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
89
90 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
91
92 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
93
| 44};
45
46/**
47 * Derived ThreadContext class for use with the Checker. The template
48 * parameter is the ThreadContext class used by the specific CPU being
49 * verified. This CheckerThreadContext is then used by the main CPU
50 * in place of its usual ThreadContext class. It handles updating the
51 * checker's state any time state is updated externally through the
52 * ThreadContext.
53 */
54template <class TC>
55class CheckerThreadContext : public ThreadContext
56{
57 public:
58 CheckerThreadContext(TC *actual_tc,
59 CheckerCPU *checker_cpu)
60 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
61 checkerCPU(checker_cpu)
62 { }
63
64 private:
65 /** The main CPU's ThreadContext, or class that implements the
66 * ThreadContext interface. */
67 TC *actualTC;
68 /** The checker's own SimpleThread. Will be updated any time
69 * anything uses this ThreadContext to externally update a
70 * thread's state. */
71 SimpleThread *checkerTC;
72 /** Pointer to the checker CPU. */
73 CheckerCPU *checkerCPU;
74
75 public:
76
77 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
78
79 void setCpuId(int id)
80 {
81 actualTC->setCpuId(id);
82 checkerTC->setCpuId(id);
83 }
84
85 int readCpuId() { return actualTC->readCpuId(); }
86
87#if FULL_SYSTEM
88 System *getSystemPtr() { return actualTC->getSystemPtr(); }
89
90 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
91
92 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
93
94 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
95
|
95
96 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
97
98 VirtualPort *getVirtPort(ThreadContext *tc = NULL)
99 { return actualTC->getVirtPort(); }
100
101 void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); }
102#else
103 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
104
105 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
106#endif
107
108 Status status() const { return actualTC->status(); }
109
110 void setStatus(Status new_status)
111 {
112 actualTC->setStatus(new_status);
113 checkerTC->setStatus(new_status);
114 }
115
116 /// Set the status to Active. Optional delay indicates number of
117 /// cycles to wait before beginning execution.
118 void activate(int delay = 1) { actualTC->activate(delay); }
119
120 /// Set the status to Suspended.
121 void suspend() { actualTC->suspend(); }
122
123 /// Set the status to Unallocated.
124 void deallocate(int delay = 0) { actualTC->deallocate(delay); }
125
126 /// Set the status to Halted.
127 void halt() { actualTC->halt(); }
128
129#if FULL_SYSTEM
130 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
131#endif
132
133 void takeOverFrom(ThreadContext *oldContext)
134 {
135 actualTC->takeOverFrom(oldContext);
136 checkerTC->copyState(oldContext);
137 }
138
139 void regStats(const std::string &name) { actualTC->regStats(name); }
140
141 void serialize(std::ostream &os) { actualTC->serialize(os); }
142 void unserialize(Checkpoint *cp, const std::string §ion)
143 { actualTC->unserialize(cp, section); }
144
145#if FULL_SYSTEM
146 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
147
148 Tick readLastActivate() { return actualTC->readLastActivate(); }
149 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
150
151 void profileClear() { return actualTC->profileClear(); }
152 void profileSample() { return actualTC->profileSample(); }
153#endif
154
155 int getThreadNum() { return actualTC->getThreadNum(); }
156
157 // @todo: Do I need this?
158 MachInst getInst() { return actualTC->getInst(); }
159
160 // @todo: Do I need this?
161 void copyArchRegs(ThreadContext *tc)
162 {
163 actualTC->copyArchRegs(tc);
164 checkerTC->copyArchRegs(tc);
165 }
166
167 void clearArchRegs()
168 {
169 actualTC->clearArchRegs();
170 checkerTC->clearArchRegs();
171 }
172
173 //
174 // New accessors for new decoder.
175 //
176 uint64_t readIntReg(int reg_idx)
177 { return actualTC->readIntReg(reg_idx); }
178
179 FloatReg readFloatReg(int reg_idx, int width)
180 { return actualTC->readFloatReg(reg_idx, width); }
181
182 FloatReg readFloatReg(int reg_idx)
183 { return actualTC->readFloatReg(reg_idx); }
184
185 FloatRegBits readFloatRegBits(int reg_idx, int width)
186 { return actualTC->readFloatRegBits(reg_idx, width); }
187
188 FloatRegBits readFloatRegBits(int reg_idx)
189 { return actualTC->readFloatRegBits(reg_idx); }
190
191 void setIntReg(int reg_idx, uint64_t val)
192 {
193 actualTC->setIntReg(reg_idx, val);
194 checkerTC->setIntReg(reg_idx, val);
195 }
196
197 void setFloatReg(int reg_idx, FloatReg val, int width)
198 {
199 actualTC->setFloatReg(reg_idx, val, width);
200 checkerTC->setFloatReg(reg_idx, val, width);
201 }
202
203 void setFloatReg(int reg_idx, FloatReg val)
204 {
205 actualTC->setFloatReg(reg_idx, val);
206 checkerTC->setFloatReg(reg_idx, val);
207 }
208
209 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
210 {
211 actualTC->setFloatRegBits(reg_idx, val, width);
212 checkerTC->setFloatRegBits(reg_idx, val, width);
213 }
214
215 void setFloatRegBits(int reg_idx, FloatRegBits val)
216 {
217 actualTC->setFloatRegBits(reg_idx, val);
218 checkerTC->setFloatRegBits(reg_idx, val);
219 }
220
221 uint64_t readPC() { return actualTC->readPC(); }
222
223 void setPC(uint64_t val)
224 {
225 actualTC->setPC(val);
226 checkerTC->setPC(val);
227 checkerCPU->recordPCChange(val);
228 }
229
230 uint64_t readNextPC() { return actualTC->readNextPC(); }
231
232 void setNextPC(uint64_t val)
233 {
234 actualTC->setNextPC(val);
235 checkerTC->setNextPC(val);
236 checkerCPU->recordNextPCChange(val);
237 }
238
239 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
240
241 void setNextNPC(uint64_t val)
242 {
243 actualTC->setNextNPC(val);
244 checkerTC->setNextNPC(val);
245 checkerCPU->recordNextPCChange(val);
246 }
247
248 MiscReg readMiscReg(int misc_reg)
249 { return actualTC->readMiscReg(misc_reg); }
250
251 MiscReg readMiscRegWithEffect(int misc_reg)
252 { return actualTC->readMiscRegWithEffect(misc_reg); }
253
254 void setMiscReg(int misc_reg, const MiscReg &val)
255 {
256 checkerTC->setMiscReg(misc_reg, val);
257 actualTC->setMiscReg(misc_reg, val);
258 }
259
260 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
261 {
262 checkerTC->setMiscRegWithEffect(misc_reg, val);
263 actualTC->setMiscRegWithEffect(misc_reg, val);
264 }
265
266 unsigned readStCondFailures()
267 { return actualTC->readStCondFailures(); }
268
269 void setStCondFailures(unsigned sc_failures)
270 {
271 checkerTC->setStCondFailures(sc_failures);
272 actualTC->setStCondFailures(sc_failures);
273 }
274
275 // @todo: Fix this!
276 bool misspeculating() { return actualTC->misspeculating(); }
277
278#if !FULL_SYSTEM
279 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
280
281 // used to shift args for indirect syscall
282 void setSyscallArg(int i, IntReg val)
283 {
284 checkerTC->setSyscallArg(i, val);
285 actualTC->setSyscallArg(i, val);
286 }
287
288 void setSyscallReturn(SyscallReturn return_value)
289 {
290 checkerTC->setSyscallReturn(return_value);
291 actualTC->setSyscallReturn(return_value);
292 }
293
294 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
295#endif
296 void changeRegFileContext(TheISA::RegContextParam param,
297 TheISA::RegContextVal val)
298 {
299 actualTC->changeRegFileContext(param, val);
300 checkerTC->changeRegFileContext(param, val);
301 }
302};
303
304#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
| 98
99 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
100
101 VirtualPort *getVirtPort(ThreadContext *tc = NULL)
102 { return actualTC->getVirtPort(); }
103
104 void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); }
105#else
106 TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
107
108 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
109#endif
110
111 Status status() const { return actualTC->status(); }
112
113 void setStatus(Status new_status)
114 {
115 actualTC->setStatus(new_status);
116 checkerTC->setStatus(new_status);
117 }
118
119 /// Set the status to Active. Optional delay indicates number of
120 /// cycles to wait before beginning execution.
121 void activate(int delay = 1) { actualTC->activate(delay); }
122
123 /// Set the status to Suspended.
124 void suspend() { actualTC->suspend(); }
125
126 /// Set the status to Unallocated.
127 void deallocate(int delay = 0) { actualTC->deallocate(delay); }
128
129 /// Set the status to Halted.
130 void halt() { actualTC->halt(); }
131
132#if FULL_SYSTEM
133 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
134#endif
135
136 void takeOverFrom(ThreadContext *oldContext)
137 {
138 actualTC->takeOverFrom(oldContext);
139 checkerTC->copyState(oldContext);
140 }
141
142 void regStats(const std::string &name) { actualTC->regStats(name); }
143
144 void serialize(std::ostream &os) { actualTC->serialize(os); }
145 void unserialize(Checkpoint *cp, const std::string §ion)
146 { actualTC->unserialize(cp, section); }
147
148#if FULL_SYSTEM
149 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
150
151 Tick readLastActivate() { return actualTC->readLastActivate(); }
152 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
153
154 void profileClear() { return actualTC->profileClear(); }
155 void profileSample() { return actualTC->profileSample(); }
156#endif
157
158 int getThreadNum() { return actualTC->getThreadNum(); }
159
160 // @todo: Do I need this?
161 MachInst getInst() { return actualTC->getInst(); }
162
163 // @todo: Do I need this?
164 void copyArchRegs(ThreadContext *tc)
165 {
166 actualTC->copyArchRegs(tc);
167 checkerTC->copyArchRegs(tc);
168 }
169
170 void clearArchRegs()
171 {
172 actualTC->clearArchRegs();
173 checkerTC->clearArchRegs();
174 }
175
176 //
177 // New accessors for new decoder.
178 //
179 uint64_t readIntReg(int reg_idx)
180 { return actualTC->readIntReg(reg_idx); }
181
182 FloatReg readFloatReg(int reg_idx, int width)
183 { return actualTC->readFloatReg(reg_idx, width); }
184
185 FloatReg readFloatReg(int reg_idx)
186 { return actualTC->readFloatReg(reg_idx); }
187
188 FloatRegBits readFloatRegBits(int reg_idx, int width)
189 { return actualTC->readFloatRegBits(reg_idx, width); }
190
191 FloatRegBits readFloatRegBits(int reg_idx)
192 { return actualTC->readFloatRegBits(reg_idx); }
193
194 void setIntReg(int reg_idx, uint64_t val)
195 {
196 actualTC->setIntReg(reg_idx, val);
197 checkerTC->setIntReg(reg_idx, val);
198 }
199
200 void setFloatReg(int reg_idx, FloatReg val, int width)
201 {
202 actualTC->setFloatReg(reg_idx, val, width);
203 checkerTC->setFloatReg(reg_idx, val, width);
204 }
205
206 void setFloatReg(int reg_idx, FloatReg val)
207 {
208 actualTC->setFloatReg(reg_idx, val);
209 checkerTC->setFloatReg(reg_idx, val);
210 }
211
212 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
213 {
214 actualTC->setFloatRegBits(reg_idx, val, width);
215 checkerTC->setFloatRegBits(reg_idx, val, width);
216 }
217
218 void setFloatRegBits(int reg_idx, FloatRegBits val)
219 {
220 actualTC->setFloatRegBits(reg_idx, val);
221 checkerTC->setFloatRegBits(reg_idx, val);
222 }
223
224 uint64_t readPC() { return actualTC->readPC(); }
225
226 void setPC(uint64_t val)
227 {
228 actualTC->setPC(val);
229 checkerTC->setPC(val);
230 checkerCPU->recordPCChange(val);
231 }
232
233 uint64_t readNextPC() { return actualTC->readNextPC(); }
234
235 void setNextPC(uint64_t val)
236 {
237 actualTC->setNextPC(val);
238 checkerTC->setNextPC(val);
239 checkerCPU->recordNextPCChange(val);
240 }
241
242 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
243
244 void setNextNPC(uint64_t val)
245 {
246 actualTC->setNextNPC(val);
247 checkerTC->setNextNPC(val);
248 checkerCPU->recordNextPCChange(val);
249 }
250
251 MiscReg readMiscReg(int misc_reg)
252 { return actualTC->readMiscReg(misc_reg); }
253
254 MiscReg readMiscRegWithEffect(int misc_reg)
255 { return actualTC->readMiscRegWithEffect(misc_reg); }
256
257 void setMiscReg(int misc_reg, const MiscReg &val)
258 {
259 checkerTC->setMiscReg(misc_reg, val);
260 actualTC->setMiscReg(misc_reg, val);
261 }
262
263 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
264 {
265 checkerTC->setMiscRegWithEffect(misc_reg, val);
266 actualTC->setMiscRegWithEffect(misc_reg, val);
267 }
268
269 unsigned readStCondFailures()
270 { return actualTC->readStCondFailures(); }
271
272 void setStCondFailures(unsigned sc_failures)
273 {
274 checkerTC->setStCondFailures(sc_failures);
275 actualTC->setStCondFailures(sc_failures);
276 }
277
278 // @todo: Fix this!
279 bool misspeculating() { return actualTC->misspeculating(); }
280
281#if !FULL_SYSTEM
282 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
283
284 // used to shift args for indirect syscall
285 void setSyscallArg(int i, IntReg val)
286 {
287 checkerTC->setSyscallArg(i, val);
288 actualTC->setSyscallArg(i, val);
289 }
290
291 void setSyscallReturn(SyscallReturn return_value)
292 {
293 checkerTC->setSyscallReturn(return_value);
294 actualTC->setSyscallReturn(return_value);
295 }
296
297 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
298#endif
299 void changeRegFileContext(TheISA::RegContextParam param,
300 TheISA::RegContextVal val)
301 {
302 actualTC->changeRegFileContext(param, val);
303 checkerTC->changeRegFileContext(param, val);
304 }
305};
306
307#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
|