1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 45#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 46 47#include "arch/types.hh" 48#include "config/the_isa.hh" 49#include "cpu/checker/cpu.hh" 50#include "cpu/simple_thread.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Checker.hh" 53 54class EndQuiesceEvent; 55namespace TheISA { 56 namespace Kernel { 57 class Statistics; 58 }; 59 class Decoder; 60}; 61 62/** 63 * Derived ThreadContext class for use with the Checker. The template 64 * parameter is the ThreadContext class used by the specific CPU being 65 * verified. This CheckerThreadContext is then used by the main CPU 66 * in place of its usual ThreadContext class. It handles updating the 67 * checker's state any time state is updated externally through the 68 * ThreadContext. 69 */ 70template <class TC> 71class CheckerThreadContext : public ThreadContext 72{ 73 public: 74 CheckerThreadContext(TC *actual_tc, 75 CheckerCPU *checker_cpu) 76 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 77 checkerCPU(checker_cpu) 78 { } 79 80 private: 81 /** The main CPU's ThreadContext, or class that implements the 82 * ThreadContext interface. */ 83 TC *actualTC; 84 /** The checker's own SimpleThread. Will be updated any time 85 * anything uses this ThreadContext to externally update a 86 * thread's state. */ 87 SimpleThread *checkerTC; 88 /** Pointer to the checker CPU. */ 89 CheckerCPU *checkerCPU; 90 91 public: 92
| 1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 45#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 46 47#include "arch/types.hh" 48#include "config/the_isa.hh" 49#include "cpu/checker/cpu.hh" 50#include "cpu/simple_thread.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Checker.hh" 53 54class EndQuiesceEvent; 55namespace TheISA { 56 namespace Kernel { 57 class Statistics; 58 }; 59 class Decoder; 60}; 61 62/** 63 * Derived ThreadContext class for use with the Checker. The template 64 * parameter is the ThreadContext class used by the specific CPU being 65 * verified. This CheckerThreadContext is then used by the main CPU 66 * in place of its usual ThreadContext class. It handles updating the 67 * checker's state any time state is updated externally through the 68 * ThreadContext. 69 */ 70template <class TC> 71class CheckerThreadContext : public ThreadContext 72{ 73 public: 74 CheckerThreadContext(TC *actual_tc, 75 CheckerCPU *checker_cpu) 76 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 77 checkerCPU(checker_cpu) 78 { } 79 80 private: 81 /** The main CPU's ThreadContext, or class that implements the 82 * ThreadContext interface. */ 83 TC *actualTC; 84 /** The checker's own SimpleThread. Will be updated any time 85 * anything uses this ThreadContext to externally update a 86 * thread's state. */ 87 SimpleThread *checkerTC; 88 /** Pointer to the checker CPU. */ 89 CheckerCPU *checkerCPU; 90 91 public: 92
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93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
| 93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
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94
| 94
|
95 uint32_t socketId() const { return actualTC->socketId(); }
| 95 uint32_t socketId() const override { return actualTC->socketId(); }
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96
| 96
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97 int cpuId() const { return actualTC->cpuId(); }
| 97 int cpuId() const override { return actualTC->cpuId(); }
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98
| 98
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99 ContextID contextId() const { return actualTC->contextId(); }
| 99 ContextID contextId() const override { return actualTC->contextId(); }
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100
| 100
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101 void setContextId(ContextID id)
| 101 void setContextId(ContextID id)override
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102 { 103 actualTC->setContextId(id); 104 checkerTC->setContextId(id); 105 } 106 107 /** Returns this thread's ID number. */
| 102 { 103 actualTC->setContextId(id); 104 checkerTC->setContextId(id); 105 } 106 107 /** Returns this thread's ID number. */
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108 int threadId() const { return actualTC->threadId(); } 109 void setThreadId(int id)
| 108 int threadId() const override { return actualTC->threadId(); } 109 void setThreadId(int id) override
|
110 { 111 checkerTC->setThreadId(id); 112 actualTC->setThreadId(id); 113 } 114
| 110 { 111 checkerTC->setThreadId(id); 112 actualTC->setThreadId(id); 113 } 114
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115 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
| 115 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
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116
| 116
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117 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
| 117 BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
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118
| 118
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119 CheckerCPU *getCheckerCpuPtr()
| 119 CheckerCPU *getCheckerCpuPtr()override
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120 { 121 return checkerCPU; 122 } 123
| 120 { 121 return checkerCPU; 122 } 123
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124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
| 124 TheISA::Decoder *getDecoderPtr() override { 125 return actualTC->getDecoderPtr(); 126 }
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125
| 127
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126 System *getSystemPtr() { return actualTC->getSystemPtr(); }
| 128 System *getSystemPtr() override { return actualTC->getSystemPtr(); }
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127
| 129
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128 TheISA::Kernel::Statistics *getKernelStats()
| 130 TheISA::Kernel::Statistics *getKernelStats()override
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129 { return actualTC->getKernelStats(); } 130
| 131 { return actualTC->getKernelStats(); } 132
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131 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
| 133 Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
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132
| 134
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133 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
| 135 void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
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134
| 136
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135 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
| 137 PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
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136
| 138
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137 FSTranslatingPortProxy &getVirtProxy()
| 139 FSTranslatingPortProxy &getVirtProxy() override
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138 { return actualTC->getVirtProxy(); } 139
| 140 { return actualTC->getVirtProxy(); } 141
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140 void initMemProxies(ThreadContext *tc)
| 142 void initMemProxies(ThreadContext *tc) override
|
141 { actualTC->initMemProxies(tc); } 142 143 void connectMemPorts(ThreadContext *tc) 144 { 145 actualTC->connectMemPorts(tc); 146 } 147
| 143 { actualTC->initMemProxies(tc); } 144 145 void connectMemPorts(ThreadContext *tc) 146 { 147 actualTC->connectMemPorts(tc); 148 } 149
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148 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
| 150 SETranslatingPortProxy &getMemProxy() override { 151 return actualTC->getMemProxy(); 152 }
|
149 150 /** Executes a syscall in SE mode. */
| 153 154 /** Executes a syscall in SE mode. */
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151 void syscall(int64_t callnum, Fault *fault)
| 155 void syscall(int64_t callnum, Fault *fault)override
|
152 { return actualTC->syscall(callnum, fault); } 153
| 156 { return actualTC->syscall(callnum, fault); } 157
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154 Status status() const { return actualTC->status(); }
| 158 Status status() const override { return actualTC->status(); }
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155
| 159
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156 void setStatus(Status new_status)
| 160 void setStatus(Status new_status) override
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157 { 158 actualTC->setStatus(new_status); 159 checkerTC->setStatus(new_status); 160 } 161 162 /// Set the status to Active.
| 161 { 162 actualTC->setStatus(new_status); 163 checkerTC->setStatus(new_status); 164 } 165 166 /// Set the status to Active.
|
163 void activate() { actualTC->activate(); }
| 167 void activate() override { actualTC->activate(); }
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164 165 /// Set the status to Suspended.
| 168 169 /// Set the status to Suspended.
|
166 void suspend() { actualTC->suspend(); }
| 170 void suspend() override{ actualTC->suspend(); }
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167 168 /// Set the status to Halted.
| 171 172 /// Set the status to Halted.
|
169 void halt() { actualTC->halt(); }
| 173 void halt() override{ actualTC->halt(); }
|
170
| 174
|
171 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
| 175 void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); }
|
172
| 176
|
173 void takeOverFrom(ThreadContext *oldContext)
| 177 void takeOverFrom(ThreadContext *oldContext) override
|
174 { 175 actualTC->takeOverFrom(oldContext); 176 checkerTC->copyState(oldContext); 177 } 178
| 178 { 179 actualTC->takeOverFrom(oldContext); 180 checkerTC->copyState(oldContext); 181 } 182
|
179 void regStats(const std::string &name)
| 183 void regStats(const std::string &name) override
|
180 { 181 actualTC->regStats(name); 182 checkerTC->regStats(name); 183 } 184
| 184 { 185 actualTC->regStats(name); 186 checkerTC->regStats(name); 187 } 188
|
185 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
| 189 EndQuiesceEvent *getQuiesceEvent() override { 190 return actualTC->getQuiesceEvent(); 191 }
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186
| 192
|
187 Tick readLastActivate() { return actualTC->readLastActivate(); } 188 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
| 193 Tick readLastActivate() override{ return actualTC->readLastActivate(); } 194 Tick readLastSuspend() override{ return actualTC->readLastSuspend(); }
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189
| 195
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190 void profileClear() { return actualTC->profileClear(); } 191 void profileSample() { return actualTC->profileSample(); }
| 196 void profileClear() override{ return actualTC->profileClear(); } 197 void profileSample() override{ return actualTC->profileSample(); }
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192 193 // @todo: Do I need this?
| 198 199 // @todo: Do I need this?
|
194 void copyArchRegs(ThreadContext *tc)
| 200 void copyArchRegs(ThreadContext *tc) override
|
195 { 196 actualTC->copyArchRegs(tc); 197 checkerTC->copyArchRegs(tc); 198 } 199
| 201 { 202 actualTC->copyArchRegs(tc); 203 checkerTC->copyArchRegs(tc); 204 } 205
|
200 void clearArchRegs()
| 206 void clearArchRegs() override
|
201 { 202 actualTC->clearArchRegs(); 203 checkerTC->clearArchRegs(); 204 } 205 206 // 207 // New accessors for new decoder. 208 //
| 207 { 208 actualTC->clearArchRegs(); 209 checkerTC->clearArchRegs(); 210 } 211 212 // 213 // New accessors for new decoder. 214 //
|
209 RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
| 215 RegVal readIntReg(int reg_idx) override { 216 return actualTC->readIntReg(reg_idx); 217 }
|
210 211 RegVal
| 218 219 RegVal
|
212 readFloatReg(int reg_idx)
| 220 readFloatReg(int reg_idx) override
|
213 { 214 return actualTC->readFloatReg(reg_idx); 215 } 216
| 221 { 222 return actualTC->readFloatReg(reg_idx); 223 } 224
|
217 const VecRegContainer& readVecReg(const RegId& reg) const
| 225 const VecRegContainer& readVecReg (const RegId& reg) const override
|
218 { return actualTC->readVecReg(reg); } 219 220 /** 221 * Read vector register for modification, hierarchical indexing. 222 */
| 226 { return actualTC->readVecReg(reg); } 227 228 /** 229 * Read vector register for modification, hierarchical indexing. 230 */
|
223 VecRegContainer& getWritableVecReg(const RegId& reg)
| 231 VecRegContainer& getWritableVecReg (const RegId& reg) override
|
224 { return actualTC->getWritableVecReg(reg); } 225 226 /** Vector Register Lane Interfaces. */ 227 /** @{ */ 228 /** Reads source vector 8bit operand. */ 229 ConstVecLane8
| 232 { return actualTC->getWritableVecReg(reg); } 233 234 /** Vector Register Lane Interfaces. */ 235 /** @{ */ 236 /** Reads source vector 8bit operand. */ 237 ConstVecLane8
|
230 readVec8BitLaneReg(const RegId& reg) const
| 238 readVec8BitLaneReg(const RegId& reg) const override
|
231 { return actualTC->readVec8BitLaneReg(reg); } 232 233 /** Reads source vector 16bit operand. */ 234 ConstVecLane16
| 239 { return actualTC->readVec8BitLaneReg(reg); } 240 241 /** Reads source vector 16bit operand. */ 242 ConstVecLane16
|
235 readVec16BitLaneReg(const RegId& reg) const
| 243 readVec16BitLaneReg(const RegId& reg) const override
|
236 { return actualTC->readVec16BitLaneReg(reg); } 237 238 /** Reads source vector 32bit operand. */ 239 ConstVecLane32
| 244 { return actualTC->readVec16BitLaneReg(reg); } 245 246 /** Reads source vector 32bit operand. */ 247 ConstVecLane32
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240 readVec32BitLaneReg(const RegId& reg) const
| 248 readVec32BitLaneReg(const RegId& reg) const override
|
241 { return actualTC->readVec32BitLaneReg(reg); } 242 243 /** Reads source vector 64bit operand. */ 244 ConstVecLane64
| 249 { return actualTC->readVec32BitLaneReg(reg); } 250 251 /** Reads source vector 64bit operand. */ 252 ConstVecLane64
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245 readVec64BitLaneReg(const RegId& reg) const
| 253 readVec64BitLaneReg(const RegId& reg) const override
|
246 { return actualTC->readVec64BitLaneReg(reg); } 247 248 /** Write a lane of the destination vector register. */ 249 virtual void setVecLane(const RegId& reg,
| 254 { return actualTC->readVec64BitLaneReg(reg); } 255 256 /** Write a lane of the destination vector register. */ 257 virtual void setVecLane(const RegId& reg,
|
250 const LaneData& val)
| 258 const LaneData<LaneSize::Byte>& val) override
|
251 { return actualTC->setVecLane(reg, val); } 252 virtual void setVecLane(const RegId& reg,
| 259 { return actualTC->setVecLane(reg, val); } 260 virtual void setVecLane(const RegId& reg,
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253 const LaneData& val)
| 261 const LaneData<LaneSize::TwoByte>& val) override
|
254 { return actualTC->setVecLane(reg, val); } 255 virtual void setVecLane(const RegId& reg,
| 262 { return actualTC->setVecLane(reg, val); } 263 virtual void setVecLane(const RegId& reg,
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256 const LaneData& val)
| 264 const LaneData<LaneSize::FourByte>& val) override
|
257 { return actualTC->setVecLane(reg, val); } 258 virtual void setVecLane(const RegId& reg,
| 265 { return actualTC->setVecLane(reg, val); } 266 virtual void setVecLane(const RegId& reg,
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259 const LaneData& val)
| 267 const LaneData<LaneSize::EightByte>& val) override
|
260 { return actualTC->setVecLane(reg, val); } 261 /** @} */ 262
| 268 { return actualTC->setVecLane(reg, val); } 269 /** @} */ 270
|
263 const VecElem& readVecElem(const RegId& reg) const
| 271 const VecElem& readVecElem(const RegId& reg) const override
|
264 { return actualTC->readVecElem(reg); } 265 266 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 267 { return actualTC->readVecPredReg(reg); } 268 269 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 270 { return actualTC->getWritableVecPredReg(reg); } 271
| 272 { return actualTC->readVecElem(reg); } 273 274 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 275 { return actualTC->readVecPredReg(reg); } 276 277 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 278 { return actualTC->getWritableVecPredReg(reg); } 279
|
272 RegVal readCCReg(int reg_idx)
| 280 RegVal readCCReg(int reg_idx) override
|
273 { return actualTC->readCCReg(reg_idx); } 274 275 void
| 281 { return actualTC->readCCReg(reg_idx); } 282 283 void
|
276 setIntReg(int reg_idx, RegVal val)
| 284 setIntReg(int reg_idx, RegVal val) override
|
277 { 278 actualTC->setIntReg(reg_idx, val); 279 checkerTC->setIntReg(reg_idx, val); 280 } 281 282 void
| 285 { 286 actualTC->setIntReg(reg_idx, val); 287 checkerTC->setIntReg(reg_idx, val); 288 } 289 290 void
|
283 setFloatReg(int reg_idx, RegVal val)
| 291 setFloatReg(int reg_idx, RegVal val) override
|
284 { 285 actualTC->setFloatReg(reg_idx, val); 286 checkerTC->setFloatReg(reg_idx, val); 287 } 288 289 void
| 292 { 293 actualTC->setFloatReg(reg_idx, val); 294 checkerTC->setFloatReg(reg_idx, val); 295 } 296 297 void
|
290 setVecReg(const RegId& reg, const VecRegContainer& val)
| 298 setVecReg(const RegId& reg, const VecRegContainer& val) override
|
291 { 292 actualTC->setVecReg(reg, val); 293 checkerTC->setVecReg(reg, val); 294 } 295 296 void
| 299 { 300 actualTC->setVecReg(reg, val); 301 checkerTC->setVecReg(reg, val); 302 } 303 304 void
|
297 setVecElem(const RegId& reg, const VecElem& val)
| 305 setVecElem(const RegId& reg, const VecElem& val) override
|
298 { 299 actualTC->setVecElem(reg, val); 300 checkerTC->setVecElem(reg, val); 301 } 302 303 void
| 306 { 307 actualTC->setVecElem(reg, val); 308 checkerTC->setVecElem(reg, val); 309 } 310 311 void
|
304 setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
| 312 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
|
305 { 306 actualTC->setVecPredReg(reg, val); 307 checkerTC->setVecPredReg(reg, val); 308 } 309 310 void
| 313 { 314 actualTC->setVecPredReg(reg, val); 315 checkerTC->setVecPredReg(reg, val); 316 } 317 318 void
|
311 setCCReg(int reg_idx, RegVal val)
| 319 setCCReg(int reg_idx, RegVal val) override
|
312 { 313 actualTC->setCCReg(reg_idx, val); 314 checkerTC->setCCReg(reg_idx, val); 315 } 316 317 /** Reads this thread's PC state. */
| 320 { 321 actualTC->setCCReg(reg_idx, val); 322 checkerTC->setCCReg(reg_idx, val); 323 } 324 325 /** Reads this thread's PC state. */
|
318 TheISA::PCState pcState()
| 326 TheISA::PCState pcState() override
|
319 { return actualTC->pcState(); } 320 321 /** Sets this thread's PC state. */ 322 void
| 327 { return actualTC->pcState(); } 328 329 /** Sets this thread's PC state. */ 330 void
|
323 pcState(const TheISA::PCState &val)
| 331 pcState(const TheISA::PCState &val) override
|
324 { 325 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 326 val, checkerTC->pcState()); 327 checkerTC->pcState(val); 328 checkerCPU->recordPCChange(val); 329 return actualTC->pcState(val); 330 } 331 332 void 333 setNPC(Addr val) 334 { 335 checkerTC->setNPC(val); 336 actualTC->setNPC(val); 337 } 338 339 void
| 332 { 333 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 334 val, checkerTC->pcState()); 335 checkerTC->pcState(val); 336 checkerCPU->recordPCChange(val); 337 return actualTC->pcState(val); 338 } 339 340 void 341 setNPC(Addr val) 342 { 343 checkerTC->setNPC(val); 344 actualTC->setNPC(val); 345 } 346 347 void
|
340 pcStateNoRecord(const TheISA::PCState &val)
| 348 pcStateNoRecord(const TheISA::PCState &val) override
|
341 { 342 return actualTC->pcState(val); 343 } 344 345 /** Reads this thread's PC. */
| 349 { 350 return actualTC->pcState(val); 351 } 352 353 /** Reads this thread's PC. */
|
346 Addr instAddr()
| 354 Addr instAddr() override
|
347 { return actualTC->instAddr(); } 348 349 /** Reads this thread's next PC. */
| 355 { return actualTC->instAddr(); } 356 357 /** Reads this thread's next PC. */
|
350 Addr nextInstAddr()
| 358 Addr nextInstAddr() override
|
351 { return actualTC->nextInstAddr(); } 352 353 /** Reads this thread's next PC. */
| 359 { return actualTC->nextInstAddr(); } 360 361 /** Reads this thread's next PC. */
|
354 MicroPC microPC()
| 362 MicroPC microPC() override
|
355 { return actualTC->microPC(); } 356
| 363 { return actualTC->microPC(); } 364
|
357 RegVal readMiscRegNoEffect(int misc_reg) const
| 365 RegVal readMiscRegNoEffect(int misc_reg) const override
|
358 { return actualTC->readMiscRegNoEffect(misc_reg); } 359
| 366 { return actualTC->readMiscRegNoEffect(misc_reg); } 367
|
360 RegVal readMiscReg(int misc_reg)
| 368 RegVal readMiscReg(int misc_reg) override
|
361 { return actualTC->readMiscReg(misc_reg); } 362 363 void
| 369 { return actualTC->readMiscReg(misc_reg); } 370 371 void
|
364 setMiscRegNoEffect(int misc_reg, RegVal val)
| 372 setMiscRegNoEffect(int misc_reg, RegVal val) override
|
365 { 366 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 367 " and O3..\n", misc_reg); 368 checkerTC->setMiscRegNoEffect(misc_reg, val); 369 actualTC->setMiscRegNoEffect(misc_reg, val); 370 } 371 372 void
| 373 { 374 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 375 " and O3..\n", misc_reg); 376 checkerTC->setMiscRegNoEffect(misc_reg, val); 377 actualTC->setMiscRegNoEffect(misc_reg, val); 378 } 379 380 void
|
373 setMiscReg(int misc_reg, RegVal val)
| 381 setMiscReg(int misc_reg, RegVal val) override
|
374 { 375 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 376 " and O3..\n", misc_reg); 377 checkerTC->setMiscReg(misc_reg, val); 378 actualTC->setMiscReg(misc_reg, val); 379 } 380 381 RegId
| 382 { 383 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 384 " and O3..\n", misc_reg); 385 checkerTC->setMiscReg(misc_reg, val); 386 actualTC->setMiscReg(misc_reg, val); 387 } 388 389 RegId
|
382 flattenRegId(const RegId& regId) const
| 390 flattenRegId(const RegId& regId) const override
|
383 { 384 return actualTC->flattenRegId(regId); 385 } 386
| 391 { 392 return actualTC->flattenRegId(regId); 393 } 394
|
387 unsigned readStCondFailures()
| 395 unsigned readStCondFailures() override
|
388 { return actualTC->readStCondFailures(); } 389 390 void
| 396 { return actualTC->readStCondFailures(); } 397 398 void
|
391 setStCondFailures(unsigned sc_failures)
| 399 setStCondFailures(unsigned sc_failures) override
|
392 { 393 actualTC->setStCondFailures(sc_failures); 394 } 395
| 400 { 401 actualTC->setStCondFailures(sc_failures); 402 } 403
|
396 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
| 404 Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
|
397
| 405
|
398 RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
| 406 RegVal readIntRegFlat(int idx) override { 407 return actualTC->readIntRegFlat(idx); 408 }
|
399 400 void
| 409 410 void
|
401 setIntRegFlat(int idx, RegVal val)
| 411 setIntRegFlat(int idx, RegVal val) override
|
402 { 403 actualTC->setIntRegFlat(idx, val); 404 } 405 406 RegVal
| 412 { 413 actualTC->setIntRegFlat(idx, val); 414 } 415 416 RegVal
|
407 readFloatRegFlat(int idx)
| 417 readFloatRegFlat(int idx) override
|
408 { 409 return actualTC->readFloatRegFlat(idx); 410 } 411 412 void
| 418 { 419 return actualTC->readFloatRegFlat(idx); 420 } 421 422 void
|
413 setFloatRegFlat(int idx, RegVal val)
| 423 setFloatRegFlat(int idx, RegVal val) override
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414 { 415 actualTC->setFloatRegFlat(idx, val); 416 } 417 418 const VecRegContainer &
| 424 { 425 actualTC->setFloatRegFlat(idx, val); 426 } 427 428 const VecRegContainer &
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419 readVecRegFlat(int idx) const
| 429 readVecRegFlat(int idx) const override
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420 { 421 return actualTC->readVecRegFlat(idx); 422 } 423 424 /** 425 * Read vector register for modification, flat indexing. 426 */ 427 VecRegContainer &
| 430 { 431 return actualTC->readVecRegFlat(idx); 432 } 433 434 /** 435 * Read vector register for modification, flat indexing. 436 */ 437 VecRegContainer &
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428 getWritableVecRegFlat(int idx)
| 438 getWritableVecRegFlat(int idx) override
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429 { 430 return actualTC->getWritableVecRegFlat(idx); 431 } 432
| 439 { 440 return actualTC->getWritableVecRegFlat(idx); 441 } 442
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433 void setVecRegFlat(int idx, const VecRegContainer& val)
| 443 void setVecRegFlat(int idx, const VecRegContainer& val) override
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434 { actualTC->setVecRegFlat(idx, val); } 435 436 const VecElem& readVecElemFlat(const RegIndex& idx,
| 444 { actualTC->setVecRegFlat(idx, val); } 445 446 const VecElem& readVecElemFlat(const RegIndex& idx,
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437 const ElemIndex& elem_idx) const
| 447 const ElemIndex& elem_idx) const override
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438 { return actualTC->readVecElemFlat(idx, elem_idx); } 439 440 void setVecElemFlat(const RegIndex& idx,
| 448 { return actualTC->readVecElemFlat(idx, elem_idx); } 449 450 void setVecElemFlat(const RegIndex& idx,
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441 const ElemIndex& elem_idx, const VecElem& val)
| 451 const ElemIndex& elem_idx, const VecElem& val) override
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442 { actualTC->setVecElemFlat(idx, elem_idx, val); } 443 444 const VecPredRegContainer& readVecPredRegFlat(int idx) const override 445 { return actualTC->readVecPredRegFlat(idx); } 446 447 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 448 { return actualTC->getWritableVecPredRegFlat(idx); } 449 450 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 451 { actualTC->setVecPredRegFlat(idx, val); } 452
| 452 { actualTC->setVecElemFlat(idx, elem_idx, val); } 453 454 const VecPredRegContainer& readVecPredRegFlat(int idx) const override 455 { return actualTC->readVecPredRegFlat(idx); } 456 457 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 458 { return actualTC->getWritableVecPredRegFlat(idx); } 459 460 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 461 { actualTC->setVecPredRegFlat(idx, val); } 462
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453 RegVal readCCRegFlat(int idx)
| 463 RegVal readCCRegFlat(int idx) override
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454 { return actualTC->readCCRegFlat(idx); } 455
| 464 { return actualTC->readCCRegFlat(idx); } 465
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456 void setCCRegFlat(int idx, RegVal val)
| 466 void setCCRegFlat(int idx, RegVal val) override
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457 { actualTC->setCCRegFlat(idx, val); } 458}; 459 460#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
| 467 { actualTC->setCCRegFlat(idx, val); } 468}; 469 470#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
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