1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56 namespace Kernel {
57 class Statistics;
58 };
59 class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker. The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified. This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class. It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73 public:
74 CheckerThreadContext(TC *actual_tc,
75 CheckerCPU *checker_cpu)
76 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77 checkerCPU(checker_cpu)
78 { }
79
80 private:
81 /** The main CPU's ThreadContext, or class that implements the
82 * ThreadContext interface. */
83 TC *actualTC;
84 /** The checker's own SimpleThread. Will be updated any time
85 * anything uses this ThreadContext to externally update a
86 * thread's state. */
87 SimpleThread *checkerTC;
88 /** Pointer to the checker CPU. */
89 CheckerCPU *checkerCPU;
90
91 public:
92
93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const { return actualTC->socketId(); }
96
97 int cpuId() const { return actualTC->cpuId(); }
98
99 ContextID contextId() const { return actualTC->contextId(); }
100
101 void setContextId(ContextID id)
102 {
103 actualTC->setContextId(id);
104 checkerTC->setContextId(id);
105 }
106
107 /** Returns this thread's ID number. */
108 int threadId() const { return actualTC->threadId(); }
109 void setThreadId(int id)
110 {
111 checkerTC->setThreadId(id);
112 actualTC->setThreadId(id);
113 }
114
115 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119 CheckerCPU *getCheckerCpuPtr()
120 {
121 return checkerCPU;
122 }
123
124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126 System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128 TheISA::Kernel::Statistics *getKernelStats()
129 { return actualTC->getKernelStats(); }
130
131 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
133 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
134
135 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
136
137 FSTranslatingPortProxy &getVirtProxy()
138 { return actualTC->getVirtProxy(); }
139
140 void initMemProxies(ThreadContext *tc)
141 { actualTC->initMemProxies(tc); }
142
143 void connectMemPorts(ThreadContext *tc)
144 {
145 actualTC->connectMemPorts(tc);
146 }
147
148 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
149
150 /** Executes a syscall in SE mode. */
151 void syscall(int64_t callnum, Fault *fault)
152 { return actualTC->syscall(callnum, fault); }
153
154 Status status() const { return actualTC->status(); }
155
156 void setStatus(Status new_status)
157 {
158 actualTC->setStatus(new_status);
159 checkerTC->setStatus(new_status);
160 }
161
162 /// Set the status to Active.
163 void activate() { actualTC->activate(); }
164
165 /// Set the status to Suspended.
166 void suspend() { actualTC->suspend(); }
167
168 /// Set the status to Halted.
169 void halt() { actualTC->halt(); }
170
171 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
172
173 void takeOverFrom(ThreadContext *oldContext)
174 {
175 actualTC->takeOverFrom(oldContext);
176 checkerTC->copyState(oldContext);
177 }
178
179 void regStats(const std::string &name)
180 {
181 actualTC->regStats(name);
182 checkerTC->regStats(name);
183 }
184
185 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
186
187 Tick readLastActivate() { return actualTC->readLastActivate(); }
188 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
189
190 void profileClear() { return actualTC->profileClear(); }
191 void profileSample() { return actualTC->profileSample(); }
192
193 // @todo: Do I need this?
194 void copyArchRegs(ThreadContext *tc)
195 {
196 actualTC->copyArchRegs(tc);
197 checkerTC->copyArchRegs(tc);
198 }
199
200 void clearArchRegs()
201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
209 RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
210
211 RegVal
212 readFloatRegBits(int reg_idx)
213 {
214 return actualTC->readFloatRegBits(reg_idx);
215 }
216
217 const VecRegContainer& readVecReg(const RegId& reg) const
218 { return actualTC->readVecReg(reg); }
219
220 /**
221 * Read vector register for modification, hierarchical indexing.
222 */
223 VecRegContainer& getWritableVecReg(const RegId& reg)
224 { return actualTC->getWritableVecReg(reg); }
225
226 /** Vector Register Lane Interfaces. */
227 /** @{ */
228 /** Reads source vector 8bit operand. */
229 ConstVecLane8
230 readVec8BitLaneReg(const RegId& reg) const
231 { return actualTC->readVec8BitLaneReg(reg); }
232
233 /** Reads source vector 16bit operand. */
234 ConstVecLane16
235 readVec16BitLaneReg(const RegId& reg) const
236 { return actualTC->readVec16BitLaneReg(reg); }
237
238 /** Reads source vector 32bit operand. */
239 ConstVecLane32
240 readVec32BitLaneReg(const RegId& reg) const
241 { return actualTC->readVec32BitLaneReg(reg); }
242
243 /** Reads source vector 64bit operand. */
244 ConstVecLane64
245 readVec64BitLaneReg(const RegId& reg) const
246 { return actualTC->readVec64BitLaneReg(reg); }
247
248 /** Write a lane of the destination vector register. */
249 virtual void setVecLane(const RegId& reg,
250 const LaneData<LaneSize::Byte>& val)
251 { return actualTC->setVecLane(reg, val); }
252 virtual void setVecLane(const RegId& reg,
253 const LaneData<LaneSize::TwoByte>& val)
254 { return actualTC->setVecLane(reg, val); }
255 virtual void setVecLane(const RegId& reg,
256 const LaneData<LaneSize::FourByte>& val)
257 { return actualTC->setVecLane(reg, val); }
258 virtual void setVecLane(const RegId& reg,
259 const LaneData<LaneSize::EightByte>& val)
260 { return actualTC->setVecLane(reg, val); }
261 /** @} */
262
263 const VecElem& readVecElem(const RegId& reg) const
264 { return actualTC->readVecElem(reg); }
265
266 CCReg readCCReg(int reg_idx)
267 { return actualTC->readCCReg(reg_idx); }
268
269 void
270 setIntReg(int reg_idx, RegVal val)
271 {
272 actualTC->setIntReg(reg_idx, val);
273 checkerTC->setIntReg(reg_idx, val);
274 }
275
276 void
277 setFloatRegBits(int reg_idx, RegVal val)
278 {
279 actualTC->setFloatRegBits(reg_idx, val);
280 checkerTC->setFloatRegBits(reg_idx, val);
281 }
282
283 void
284 setVecReg(const RegId& reg, const VecRegContainer& val)
285 {
286 actualTC->setVecReg(reg, val);
287 checkerTC->setVecReg(reg, val);
288 }
289
290 void
291 setVecElem(const RegId& reg, const VecElem& val)
292 {
293 actualTC->setVecElem(reg, val);
294 checkerTC->setVecElem(reg, val);
295 }
296
297 void
298 setCCReg(int reg_idx, CCReg val)
299 {
300 actualTC->setCCReg(reg_idx, val);
301 checkerTC->setCCReg(reg_idx, val);
302 }
303
304 /** Reads this thread's PC state. */
305 TheISA::PCState pcState()
306 { return actualTC->pcState(); }
307
308 /** Sets this thread's PC state. */
309 void
310 pcState(const TheISA::PCState &val)
311 {
312 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
313 val, checkerTC->pcState());
314 checkerTC->pcState(val);
315 checkerCPU->recordPCChange(val);
316 return actualTC->pcState(val);
317 }
318
319 void
320 setNPC(Addr val)
321 {
322 checkerTC->setNPC(val);
323 actualTC->setNPC(val);
324 }
325
326 void
327 pcStateNoRecord(const TheISA::PCState &val)
328 {
329 return actualTC->pcState(val);
330 }
331
332 /** Reads this thread's PC. */
333 Addr instAddr()
334 { return actualTC->instAddr(); }
335
336 /** Reads this thread's next PC. */
337 Addr nextInstAddr()
338 { return actualTC->nextInstAddr(); }
339
340 /** Reads this thread's next PC. */
341 MicroPC microPC()
342 { return actualTC->microPC(); }
343
344 RegVal readMiscRegNoEffect(int misc_reg) const
345 { return actualTC->readMiscRegNoEffect(misc_reg); }
346
347 RegVal readMiscReg(int misc_reg)
348 { return actualTC->readMiscReg(misc_reg); }
349
350 void
| 1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56 namespace Kernel {
57 class Statistics;
58 };
59 class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker. The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified. This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class. It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73 public:
74 CheckerThreadContext(TC *actual_tc,
75 CheckerCPU *checker_cpu)
76 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77 checkerCPU(checker_cpu)
78 { }
79
80 private:
81 /** The main CPU's ThreadContext, or class that implements the
82 * ThreadContext interface. */
83 TC *actualTC;
84 /** The checker's own SimpleThread. Will be updated any time
85 * anything uses this ThreadContext to externally update a
86 * thread's state. */
87 SimpleThread *checkerTC;
88 /** Pointer to the checker CPU. */
89 CheckerCPU *checkerCPU;
90
91 public:
92
93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const { return actualTC->socketId(); }
96
97 int cpuId() const { return actualTC->cpuId(); }
98
99 ContextID contextId() const { return actualTC->contextId(); }
100
101 void setContextId(ContextID id)
102 {
103 actualTC->setContextId(id);
104 checkerTC->setContextId(id);
105 }
106
107 /** Returns this thread's ID number. */
108 int threadId() const { return actualTC->threadId(); }
109 void setThreadId(int id)
110 {
111 checkerTC->setThreadId(id);
112 actualTC->setThreadId(id);
113 }
114
115 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119 CheckerCPU *getCheckerCpuPtr()
120 {
121 return checkerCPU;
122 }
123
124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126 System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128 TheISA::Kernel::Statistics *getKernelStats()
129 { return actualTC->getKernelStats(); }
130
131 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
133 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
134
135 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
136
137 FSTranslatingPortProxy &getVirtProxy()
138 { return actualTC->getVirtProxy(); }
139
140 void initMemProxies(ThreadContext *tc)
141 { actualTC->initMemProxies(tc); }
142
143 void connectMemPorts(ThreadContext *tc)
144 {
145 actualTC->connectMemPorts(tc);
146 }
147
148 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
149
150 /** Executes a syscall in SE mode. */
151 void syscall(int64_t callnum, Fault *fault)
152 { return actualTC->syscall(callnum, fault); }
153
154 Status status() const { return actualTC->status(); }
155
156 void setStatus(Status new_status)
157 {
158 actualTC->setStatus(new_status);
159 checkerTC->setStatus(new_status);
160 }
161
162 /// Set the status to Active.
163 void activate() { actualTC->activate(); }
164
165 /// Set the status to Suspended.
166 void suspend() { actualTC->suspend(); }
167
168 /// Set the status to Halted.
169 void halt() { actualTC->halt(); }
170
171 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
172
173 void takeOverFrom(ThreadContext *oldContext)
174 {
175 actualTC->takeOverFrom(oldContext);
176 checkerTC->copyState(oldContext);
177 }
178
179 void regStats(const std::string &name)
180 {
181 actualTC->regStats(name);
182 checkerTC->regStats(name);
183 }
184
185 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
186
187 Tick readLastActivate() { return actualTC->readLastActivate(); }
188 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
189
190 void profileClear() { return actualTC->profileClear(); }
191 void profileSample() { return actualTC->profileSample(); }
192
193 // @todo: Do I need this?
194 void copyArchRegs(ThreadContext *tc)
195 {
196 actualTC->copyArchRegs(tc);
197 checkerTC->copyArchRegs(tc);
198 }
199
200 void clearArchRegs()
201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
209 RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
210
211 RegVal
212 readFloatRegBits(int reg_idx)
213 {
214 return actualTC->readFloatRegBits(reg_idx);
215 }
216
217 const VecRegContainer& readVecReg(const RegId& reg) const
218 { return actualTC->readVecReg(reg); }
219
220 /**
221 * Read vector register for modification, hierarchical indexing.
222 */
223 VecRegContainer& getWritableVecReg(const RegId& reg)
224 { return actualTC->getWritableVecReg(reg); }
225
226 /** Vector Register Lane Interfaces. */
227 /** @{ */
228 /** Reads source vector 8bit operand. */
229 ConstVecLane8
230 readVec8BitLaneReg(const RegId& reg) const
231 { return actualTC->readVec8BitLaneReg(reg); }
232
233 /** Reads source vector 16bit operand. */
234 ConstVecLane16
235 readVec16BitLaneReg(const RegId& reg) const
236 { return actualTC->readVec16BitLaneReg(reg); }
237
238 /** Reads source vector 32bit operand. */
239 ConstVecLane32
240 readVec32BitLaneReg(const RegId& reg) const
241 { return actualTC->readVec32BitLaneReg(reg); }
242
243 /** Reads source vector 64bit operand. */
244 ConstVecLane64
245 readVec64BitLaneReg(const RegId& reg) const
246 { return actualTC->readVec64BitLaneReg(reg); }
247
248 /** Write a lane of the destination vector register. */
249 virtual void setVecLane(const RegId& reg,
250 const LaneData<LaneSize::Byte>& val)
251 { return actualTC->setVecLane(reg, val); }
252 virtual void setVecLane(const RegId& reg,
253 const LaneData<LaneSize::TwoByte>& val)
254 { return actualTC->setVecLane(reg, val); }
255 virtual void setVecLane(const RegId& reg,
256 const LaneData<LaneSize::FourByte>& val)
257 { return actualTC->setVecLane(reg, val); }
258 virtual void setVecLane(const RegId& reg,
259 const LaneData<LaneSize::EightByte>& val)
260 { return actualTC->setVecLane(reg, val); }
261 /** @} */
262
263 const VecElem& readVecElem(const RegId& reg) const
264 { return actualTC->readVecElem(reg); }
265
266 CCReg readCCReg(int reg_idx)
267 { return actualTC->readCCReg(reg_idx); }
268
269 void
270 setIntReg(int reg_idx, RegVal val)
271 {
272 actualTC->setIntReg(reg_idx, val);
273 checkerTC->setIntReg(reg_idx, val);
274 }
275
276 void
277 setFloatRegBits(int reg_idx, RegVal val)
278 {
279 actualTC->setFloatRegBits(reg_idx, val);
280 checkerTC->setFloatRegBits(reg_idx, val);
281 }
282
283 void
284 setVecReg(const RegId& reg, const VecRegContainer& val)
285 {
286 actualTC->setVecReg(reg, val);
287 checkerTC->setVecReg(reg, val);
288 }
289
290 void
291 setVecElem(const RegId& reg, const VecElem& val)
292 {
293 actualTC->setVecElem(reg, val);
294 checkerTC->setVecElem(reg, val);
295 }
296
297 void
298 setCCReg(int reg_idx, CCReg val)
299 {
300 actualTC->setCCReg(reg_idx, val);
301 checkerTC->setCCReg(reg_idx, val);
302 }
303
304 /** Reads this thread's PC state. */
305 TheISA::PCState pcState()
306 { return actualTC->pcState(); }
307
308 /** Sets this thread's PC state. */
309 void
310 pcState(const TheISA::PCState &val)
311 {
312 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
313 val, checkerTC->pcState());
314 checkerTC->pcState(val);
315 checkerCPU->recordPCChange(val);
316 return actualTC->pcState(val);
317 }
318
319 void
320 setNPC(Addr val)
321 {
322 checkerTC->setNPC(val);
323 actualTC->setNPC(val);
324 }
325
326 void
327 pcStateNoRecord(const TheISA::PCState &val)
328 {
329 return actualTC->pcState(val);
330 }
331
332 /** Reads this thread's PC. */
333 Addr instAddr()
334 { return actualTC->instAddr(); }
335
336 /** Reads this thread's next PC. */
337 Addr nextInstAddr()
338 { return actualTC->nextInstAddr(); }
339
340 /** Reads this thread's next PC. */
341 MicroPC microPC()
342 { return actualTC->microPC(); }
343
344 RegVal readMiscRegNoEffect(int misc_reg) const
345 { return actualTC->readMiscRegNoEffect(misc_reg); }
346
347 RegVal readMiscReg(int misc_reg)
348 { return actualTC->readMiscReg(misc_reg); }
349
350 void
|
361 {
362 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
363 " and O3..\n", misc_reg);
364 checkerTC->setMiscReg(misc_reg, val);
365 actualTC->setMiscReg(misc_reg, val);
366 }
367
368 RegId
369 flattenRegId(const RegId& regId) const
370 {
371 return actualTC->flattenRegId(regId);
372 }
373
374 unsigned readStCondFailures()
375 { return actualTC->readStCondFailures(); }
376
377 void
378 setStCondFailures(unsigned sc_failures)
379 {
380 actualTC->setStCondFailures(sc_failures);
381 }
382
383 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
384
385 RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
386
387 void
388 setIntRegFlat(int idx, RegVal val)
389 {
390 actualTC->setIntRegFlat(idx, val);
391 }
392
393 RegVal
394 readFloatRegBitsFlat(int idx)
395 {
396 return actualTC->readFloatRegBitsFlat(idx);
397 }
398
399 void
400 setFloatRegBitsFlat(int idx, RegVal val)
401 {
402 actualTC->setFloatRegBitsFlat(idx, val);
403 }
404
405 const VecRegContainer &
406 readVecRegFlat(int idx) const
407 {
408 return actualTC->readVecRegFlat(idx);
409 }
410
411 /**
412 * Read vector register for modification, flat indexing.
413 */
414 VecRegContainer &
415 getWritableVecRegFlat(int idx)
416 {
417 return actualTC->getWritableVecRegFlat(idx);
418 }
419
420 void setVecRegFlat(int idx, const VecRegContainer& val)
421 { actualTC->setVecRegFlat(idx, val); }
422
423 const VecElem& readVecElemFlat(const RegIndex& idx,
424 const ElemIndex& elem_idx) const
425 { return actualTC->readVecElemFlat(idx, elem_idx); }
426
427 void setVecElemFlat(const RegIndex& idx,
428 const ElemIndex& elem_idx, const VecElem& val)
429 { actualTC->setVecElemFlat(idx, elem_idx, val); }
430
431 CCReg readCCRegFlat(int idx)
432 { return actualTC->readCCRegFlat(idx); }
433
434 void setCCRegFlat(int idx, CCReg val)
435 { actualTC->setCCRegFlat(idx, val); }
436};
437
438#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
| 361 {
362 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
363 " and O3..\n", misc_reg);
364 checkerTC->setMiscReg(misc_reg, val);
365 actualTC->setMiscReg(misc_reg, val);
366 }
367
368 RegId
369 flattenRegId(const RegId& regId) const
370 {
371 return actualTC->flattenRegId(regId);
372 }
373
374 unsigned readStCondFailures()
375 { return actualTC->readStCondFailures(); }
376
377 void
378 setStCondFailures(unsigned sc_failures)
379 {
380 actualTC->setStCondFailures(sc_failures);
381 }
382
383 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
384
385 RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
386
387 void
388 setIntRegFlat(int idx, RegVal val)
389 {
390 actualTC->setIntRegFlat(idx, val);
391 }
392
393 RegVal
394 readFloatRegBitsFlat(int idx)
395 {
396 return actualTC->readFloatRegBitsFlat(idx);
397 }
398
399 void
400 setFloatRegBitsFlat(int idx, RegVal val)
401 {
402 actualTC->setFloatRegBitsFlat(idx, val);
403 }
404
405 const VecRegContainer &
406 readVecRegFlat(int idx) const
407 {
408 return actualTC->readVecRegFlat(idx);
409 }
410
411 /**
412 * Read vector register for modification, flat indexing.
413 */
414 VecRegContainer &
415 getWritableVecRegFlat(int idx)
416 {
417 return actualTC->getWritableVecRegFlat(idx);
418 }
419
420 void setVecRegFlat(int idx, const VecRegContainer& val)
421 { actualTC->setVecRegFlat(idx, val); }
422
423 const VecElem& readVecElemFlat(const RegIndex& idx,
424 const ElemIndex& elem_idx) const
425 { return actualTC->readVecElemFlat(idx, elem_idx); }
426
427 void setVecElemFlat(const RegIndex& idx,
428 const ElemIndex& elem_idx, const VecElem& val)
429 { actualTC->setVecElemFlat(idx, elem_idx, val); }
430
431 CCReg readCCRegFlat(int idx)
432 { return actualTC->readCCRegFlat(idx); }
433
434 void setCCRegFlat(int idx, CCReg val)
435 { actualTC->setCCRegFlat(idx, val); }
436};
437
438#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
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