1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56 namespace Kernel {
57 class Statistics;
58 };
59 class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker. The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified. This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class. It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73 public:
74 CheckerThreadContext(TC *actual_tc,
75 CheckerCPU *checker_cpu)
76 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77 checkerCPU(checker_cpu)
78 { }
79
80 private:
81 /** The main CPU's ThreadContext, or class that implements the
82 * ThreadContext interface. */
83 TC *actualTC;
84 /** The checker's own SimpleThread. Will be updated any time
85 * anything uses this ThreadContext to externally update a
86 * thread's state. */
87 SimpleThread *checkerTC;
88 /** Pointer to the checker CPU. */
89 CheckerCPU *checkerCPU;
90
91 public:
92
93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const { return actualTC->socketId(); }
96
97 int cpuId() const { return actualTC->cpuId(); }
98
99 ContextID contextId() const { return actualTC->contextId(); }
100
101 void setContextId(ContextID id)
102 {
103 actualTC->setContextId(id);
104 checkerTC->setContextId(id);
105 }
106
107 /** Returns this thread's ID number. */
108 int threadId() const { return actualTC->threadId(); }
109 void setThreadId(int id)
110 {
111 checkerTC->setThreadId(id);
112 actualTC->setThreadId(id);
113 }
114
115 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119 CheckerCPU *getCheckerCpuPtr()
120 {
121 return checkerCPU;
122 }
123
124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126 System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128 TheISA::Kernel::Statistics *getKernelStats()
129 { return actualTC->getKernelStats(); }
130
131 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
| 1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56 namespace Kernel {
57 class Statistics;
58 };
59 class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker. The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified. This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class. It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73 public:
74 CheckerThreadContext(TC *actual_tc,
75 CheckerCPU *checker_cpu)
76 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77 checkerCPU(checker_cpu)
78 { }
79
80 private:
81 /** The main CPU's ThreadContext, or class that implements the
82 * ThreadContext interface. */
83 TC *actualTC;
84 /** The checker's own SimpleThread. Will be updated any time
85 * anything uses this ThreadContext to externally update a
86 * thread's state. */
87 SimpleThread *checkerTC;
88 /** Pointer to the checker CPU. */
89 CheckerCPU *checkerCPU;
90
91 public:
92
93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const { return actualTC->socketId(); }
96
97 int cpuId() const { return actualTC->cpuId(); }
98
99 ContextID contextId() const { return actualTC->contextId(); }
100
101 void setContextId(ContextID id)
102 {
103 actualTC->setContextId(id);
104 checkerTC->setContextId(id);
105 }
106
107 /** Returns this thread's ID number. */
108 int threadId() const { return actualTC->threadId(); }
109 void setThreadId(int id)
110 {
111 checkerTC->setThreadId(id);
112 actualTC->setThreadId(id);
113 }
114
115 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119 CheckerCPU *getCheckerCpuPtr()
120 {
121 return checkerCPU;
122 }
123
124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126 System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128 TheISA::Kernel::Statistics *getKernelStats()
129 { return actualTC->getKernelStats(); }
130
131 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
|
| 133 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
134
|
133 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
134
135 FSTranslatingPortProxy &getVirtProxy()
136 { return actualTC->getVirtProxy(); }
137
138 void initMemProxies(ThreadContext *tc)
139 { actualTC->initMemProxies(tc); }
140
141 void connectMemPorts(ThreadContext *tc)
142 {
143 actualTC->connectMemPorts(tc);
144 }
145
146 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
147
148 /** Executes a syscall in SE mode. */
149 void syscall(int64_t callnum, Fault *fault)
150 { return actualTC->syscall(callnum, fault); }
151
152 Status status() const { return actualTC->status(); }
153
154 void setStatus(Status new_status)
155 {
156 actualTC->setStatus(new_status);
157 checkerTC->setStatus(new_status);
158 }
159
160 /// Set the status to Active.
161 void activate() { actualTC->activate(); }
162
163 /// Set the status to Suspended.
164 void suspend() { actualTC->suspend(); }
165
166 /// Set the status to Halted.
167 void halt() { actualTC->halt(); }
168
169 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
170
171 void takeOverFrom(ThreadContext *oldContext)
172 {
173 actualTC->takeOverFrom(oldContext);
174 checkerTC->copyState(oldContext);
175 }
176
177 void regStats(const std::string &name)
178 {
179 actualTC->regStats(name);
180 checkerTC->regStats(name);
181 }
182
183 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
184
185 Tick readLastActivate() { return actualTC->readLastActivate(); }
186 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
187
188 void profileClear() { return actualTC->profileClear(); }
189 void profileSample() { return actualTC->profileSample(); }
190
191 // @todo: Do I need this?
192 void copyArchRegs(ThreadContext *tc)
193 {
194 actualTC->copyArchRegs(tc);
195 checkerTC->copyArchRegs(tc);
196 }
197
198 void clearArchRegs()
199 {
200 actualTC->clearArchRegs();
201 checkerTC->clearArchRegs();
202 }
203
204 //
205 // New accessors for new decoder.
206 //
207 uint64_t readIntReg(int reg_idx)
208 { return actualTC->readIntReg(reg_idx); }
209
210 FloatReg readFloatReg(int reg_idx)
211 { return actualTC->readFloatReg(reg_idx); }
212
213 FloatRegBits readFloatRegBits(int reg_idx)
214 { return actualTC->readFloatRegBits(reg_idx); }
215
216 CCReg readCCReg(int reg_idx)
217 { return actualTC->readCCReg(reg_idx); }
218
219 void setIntReg(int reg_idx, uint64_t val)
220 {
221 actualTC->setIntReg(reg_idx, val);
222 checkerTC->setIntReg(reg_idx, val);
223 }
224
225 void setFloatReg(int reg_idx, FloatReg val)
226 {
227 actualTC->setFloatReg(reg_idx, val);
228 checkerTC->setFloatReg(reg_idx, val);
229 }
230
231 void setFloatRegBits(int reg_idx, FloatRegBits val)
232 {
233 actualTC->setFloatRegBits(reg_idx, val);
234 checkerTC->setFloatRegBits(reg_idx, val);
235 }
236
237 void setCCReg(int reg_idx, CCReg val)
238 {
239 actualTC->setCCReg(reg_idx, val);
240 checkerTC->setCCReg(reg_idx, val);
241 }
242
243 /** Reads this thread's PC state. */
244 TheISA::PCState pcState()
245 { return actualTC->pcState(); }
246
247 /** Sets this thread's PC state. */
248 void pcState(const TheISA::PCState &val)
249 {
250 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
251 val, checkerTC->pcState());
252 checkerTC->pcState(val);
253 checkerCPU->recordPCChange(val);
254 return actualTC->pcState(val);
255 }
256
| 135 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
136
137 FSTranslatingPortProxy &getVirtProxy()
138 { return actualTC->getVirtProxy(); }
139
140 void initMemProxies(ThreadContext *tc)
141 { actualTC->initMemProxies(tc); }
142
143 void connectMemPorts(ThreadContext *tc)
144 {
145 actualTC->connectMemPorts(tc);
146 }
147
148 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
149
150 /** Executes a syscall in SE mode. */
151 void syscall(int64_t callnum, Fault *fault)
152 { return actualTC->syscall(callnum, fault); }
153
154 Status status() const { return actualTC->status(); }
155
156 void setStatus(Status new_status)
157 {
158 actualTC->setStatus(new_status);
159 checkerTC->setStatus(new_status);
160 }
161
162 /// Set the status to Active.
163 void activate() { actualTC->activate(); }
164
165 /// Set the status to Suspended.
166 void suspend() { actualTC->suspend(); }
167
168 /// Set the status to Halted.
169 void halt() { actualTC->halt(); }
170
171 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
172
173 void takeOverFrom(ThreadContext *oldContext)
174 {
175 actualTC->takeOverFrom(oldContext);
176 checkerTC->copyState(oldContext);
177 }
178
179 void regStats(const std::string &name)
180 {
181 actualTC->regStats(name);
182 checkerTC->regStats(name);
183 }
184
185 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
186
187 Tick readLastActivate() { return actualTC->readLastActivate(); }
188 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
189
190 void profileClear() { return actualTC->profileClear(); }
191 void profileSample() { return actualTC->profileSample(); }
192
193 // @todo: Do I need this?
194 void copyArchRegs(ThreadContext *tc)
195 {
196 actualTC->copyArchRegs(tc);
197 checkerTC->copyArchRegs(tc);
198 }
199
200 void clearArchRegs()
201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
209 uint64_t readIntReg(int reg_idx)
210 { return actualTC->readIntReg(reg_idx); }
211
212 FloatReg readFloatReg(int reg_idx)
213 { return actualTC->readFloatReg(reg_idx); }
214
215 FloatRegBits readFloatRegBits(int reg_idx)
216 { return actualTC->readFloatRegBits(reg_idx); }
217
218 CCReg readCCReg(int reg_idx)
219 { return actualTC->readCCReg(reg_idx); }
220
221 void setIntReg(int reg_idx, uint64_t val)
222 {
223 actualTC->setIntReg(reg_idx, val);
224 checkerTC->setIntReg(reg_idx, val);
225 }
226
227 void setFloatReg(int reg_idx, FloatReg val)
228 {
229 actualTC->setFloatReg(reg_idx, val);
230 checkerTC->setFloatReg(reg_idx, val);
231 }
232
233 void setFloatRegBits(int reg_idx, FloatRegBits val)
234 {
235 actualTC->setFloatRegBits(reg_idx, val);
236 checkerTC->setFloatRegBits(reg_idx, val);
237 }
238
239 void setCCReg(int reg_idx, CCReg val)
240 {
241 actualTC->setCCReg(reg_idx, val);
242 checkerTC->setCCReg(reg_idx, val);
243 }
244
245 /** Reads this thread's PC state. */
246 TheISA::PCState pcState()
247 { return actualTC->pcState(); }
248
249 /** Sets this thread's PC state. */
250 void pcState(const TheISA::PCState &val)
251 {
252 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
253 val, checkerTC->pcState());
254 checkerTC->pcState(val);
255 checkerCPU->recordPCChange(val);
256 return actualTC->pcState(val);
257 }
258
|
| 259 void setNPC(Addr val)
260 {
261 checkerTC->setNPC(val);
262 actualTC->setNPC(val);
263 }
264
|
257 void pcStateNoRecord(const TheISA::PCState &val)
258 {
259 return actualTC->pcState(val);
260 }
261
262 /** Reads this thread's PC. */
263 Addr instAddr()
264 { return actualTC->instAddr(); }
265
266 /** Reads this thread's next PC. */
267 Addr nextInstAddr()
268 { return actualTC->nextInstAddr(); }
269
270 /** Reads this thread's next PC. */
271 MicroPC microPC()
272 { return actualTC->microPC(); }
273
274 MiscReg readMiscRegNoEffect(int misc_reg) const
275 { return actualTC->readMiscRegNoEffect(misc_reg); }
276
277 MiscReg readMiscReg(int misc_reg)
278 { return actualTC->readMiscReg(misc_reg); }
279
280 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
281 {
282 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
283 " and O3..\n", misc_reg);
284 checkerTC->setMiscRegNoEffect(misc_reg, val);
285 actualTC->setMiscRegNoEffect(misc_reg, val);
286 }
287
288 void setMiscReg(int misc_reg, const MiscReg &val)
289 {
290 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
291 " and O3..\n", misc_reg);
292 checkerTC->setMiscReg(misc_reg, val);
293 actualTC->setMiscReg(misc_reg, val);
294 }
295
296 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
297 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
298 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
299 int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
300
301 unsigned readStCondFailures()
302 { return actualTC->readStCondFailures(); }
303
304 void setStCondFailures(unsigned sc_failures)
305 {
306 actualTC->setStCondFailures(sc_failures);
307 }
308
309 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
310
311 uint64_t readIntRegFlat(int idx)
312 { return actualTC->readIntRegFlat(idx); }
313
314 void setIntRegFlat(int idx, uint64_t val)
315 { actualTC->setIntRegFlat(idx, val); }
316
317 FloatReg readFloatRegFlat(int idx)
318 { return actualTC->readFloatRegFlat(idx); }
319
320 void setFloatRegFlat(int idx, FloatReg val)
321 { actualTC->setFloatRegFlat(idx, val); }
322
323 FloatRegBits readFloatRegBitsFlat(int idx)
324 { return actualTC->readFloatRegBitsFlat(idx); }
325
326 void setFloatRegBitsFlat(int idx, FloatRegBits val)
327 { actualTC->setFloatRegBitsFlat(idx, val); }
328
329 CCReg readCCRegFlat(int idx)
330 { return actualTC->readCCRegFlat(idx); }
331
332 void setCCRegFlat(int idx, CCReg val)
333 { actualTC->setCCRegFlat(idx, val); }
334};
335
336#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
| 265 void pcStateNoRecord(const TheISA::PCState &val)
266 {
267 return actualTC->pcState(val);
268 }
269
270 /** Reads this thread's PC. */
271 Addr instAddr()
272 { return actualTC->instAddr(); }
273
274 /** Reads this thread's next PC. */
275 Addr nextInstAddr()
276 { return actualTC->nextInstAddr(); }
277
278 /** Reads this thread's next PC. */
279 MicroPC microPC()
280 { return actualTC->microPC(); }
281
282 MiscReg readMiscRegNoEffect(int misc_reg) const
283 { return actualTC->readMiscRegNoEffect(misc_reg); }
284
285 MiscReg readMiscReg(int misc_reg)
286 { return actualTC->readMiscReg(misc_reg); }
287
288 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
289 {
290 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
291 " and O3..\n", misc_reg);
292 checkerTC->setMiscRegNoEffect(misc_reg, val);
293 actualTC->setMiscRegNoEffect(misc_reg, val);
294 }
295
296 void setMiscReg(int misc_reg, const MiscReg &val)
297 {
298 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
299 " and O3..\n", misc_reg);
300 checkerTC->setMiscReg(misc_reg, val);
301 actualTC->setMiscReg(misc_reg, val);
302 }
303
304 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
305 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
306 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
307 int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
308
309 unsigned readStCondFailures()
310 { return actualTC->readStCondFailures(); }
311
312 void setStCondFailures(unsigned sc_failures)
313 {
314 actualTC->setStCondFailures(sc_failures);
315 }
316
317 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
318
319 uint64_t readIntRegFlat(int idx)
320 { return actualTC->readIntRegFlat(idx); }
321
322 void setIntRegFlat(int idx, uint64_t val)
323 { actualTC->setIntRegFlat(idx, val); }
324
325 FloatReg readFloatRegFlat(int idx)
326 { return actualTC->readFloatRegFlat(idx); }
327
328 void setFloatRegFlat(int idx, FloatReg val)
329 { actualTC->setFloatRegFlat(idx, val); }
330
331 FloatRegBits readFloatRegBitsFlat(int idx)
332 { return actualTC->readFloatRegBitsFlat(idx); }
333
334 void setFloatRegBitsFlat(int idx, FloatRegBits val)
335 { actualTC->setFloatRegBitsFlat(idx, val); }
336
337 CCReg readCCRegFlat(int idx)
338 { return actualTC->readCCRegFlat(idx); }
339
340 void setCCRegFlat(int idx, CCReg val)
341 { actualTC->setCCRegFlat(idx, val); }
342};
343
344#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
|