1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56 namespace Kernel {
57 class Statistics;
58 };
59 class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker. The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified. This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class. It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73 public:
74 CheckerThreadContext(TC *actual_tc,
75 CheckerCPU *checker_cpu)
76 : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77 checkerCPU(checker_cpu)
78 { }
79
80 private:
81 /** The main CPU's ThreadContext, or class that implements the
82 * ThreadContext interface. */
83 TC *actualTC;
84 /** The checker's own SimpleThread. Will be updated any time
85 * anything uses this ThreadContext to externally update a
86 * thread's state. */
87 SimpleThread *checkerTC;
88 /** Pointer to the checker CPU. */
89 CheckerCPU *checkerCPU;
90
91 public:
92
93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95 uint32_t socketId() const { return actualTC->socketId(); }
96
97 int cpuId() const { return actualTC->cpuId(); }
98
99 int contextId() const { return actualTC->contextId(); }
100
101 void setContextId(int id)
102 {
103 actualTC->setContextId(id);
104 checkerTC->setContextId(id);
105 }
106
107 /** Returns this thread's ID number. */
108 int threadId() const { return actualTC->threadId(); }
109 void setThreadId(int id)
110 {
111 checkerTC->setThreadId(id);
112 actualTC->setThreadId(id);
113 }
114
115 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119 CheckerCPU *getCheckerCpuPtr()
120 {
121 return checkerCPU;
122 }
123
124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126 System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128 TheISA::Kernel::Statistics *getKernelStats()
129 { return actualTC->getKernelStats(); }
130
131 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
133 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
134
135 FSTranslatingPortProxy &getVirtProxy()
136 { return actualTC->getVirtProxy(); }
137
138 void initMemProxies(ThreadContext *tc)
139 { actualTC->initMemProxies(tc); }
140
141 void connectMemPorts(ThreadContext *tc)
142 {
143 actualTC->connectMemPorts(tc);
144 }
145
146 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
147
148 /** Executes a syscall in SE mode. */
149 void syscall(int64_t callnum)
150 { return actualTC->syscall(callnum); }
151
152 Status status() const { return actualTC->status(); }
153
154 void setStatus(Status new_status)
155 {
156 actualTC->setStatus(new_status);
157 checkerTC->setStatus(new_status);
158 }
159
160 /// Set the status to Active. Optional delay indicates number of
161 /// cycles to wait before beginning execution.
162 void activate(Cycles delay = Cycles(1))
163 { actualTC->activate(delay); }
164
165 /// Set the status to Suspended.
166 void suspend(Cycles delay) { actualTC->suspend(delay); }
167
168 /// Set the status to Halted.
169 void halt(Cycles delay) { actualTC->halt(delay); }
170
171 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
172
173 void takeOverFrom(ThreadContext *oldContext)
174 {
175 actualTC->takeOverFrom(oldContext);
176 checkerTC->copyState(oldContext);
177 }
178
179 void regStats(const std::string &name)
180 {
181 actualTC->regStats(name);
182 checkerTC->regStats(name);
183 }
184
185 void serialize(std::ostream &os) { actualTC->serialize(os); }
186 void unserialize(Checkpoint *cp, const std::string &section)
187 { actualTC->unserialize(cp, section); }
188
189 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
190
191 Tick readLastActivate() { return actualTC->readLastActivate(); }
192 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
193
194 void profileClear() { return actualTC->profileClear(); }
195 void profileSample() { return actualTC->profileSample(); }
196
197 // @todo: Do I need this?
198 void copyArchRegs(ThreadContext *tc)
199 {
200 actualTC->copyArchRegs(tc);
201 checkerTC->copyArchRegs(tc);
202 }
203
204 void clearArchRegs()
205 {
206 actualTC->clearArchRegs();
207 checkerTC->clearArchRegs();
208 }
209
210 //
211 // New accessors for new decoder.
212 //
213 uint64_t readIntReg(int reg_idx)
214 { return actualTC->readIntReg(reg_idx); }
215
216 FloatReg readFloatReg(int reg_idx)
217 { return actualTC->readFloatReg(reg_idx); }
218
219 FloatRegBits readFloatRegBits(int reg_idx)
220 { return actualTC->readFloatRegBits(reg_idx); }
221
222 CCReg readCCReg(int reg_idx)
223 { return actualTC->readCCReg(reg_idx); }
224
225 void setIntReg(int reg_idx, uint64_t val)
226 {
227 actualTC->setIntReg(reg_idx, val);
228 checkerTC->setIntReg(reg_idx, val);
229 }
230
231 void setFloatReg(int reg_idx, FloatReg val)
232 {
233 actualTC->setFloatReg(reg_idx, val);
234 checkerTC->setFloatReg(reg_idx, val);
235 }
236
237 void setFloatRegBits(int reg_idx, FloatRegBits val)
238 {
239 actualTC->setFloatRegBits(reg_idx, val);
240 checkerTC->setFloatRegBits(reg_idx, val);
241 }
242
243 void setCCReg(int reg_idx, CCReg val)
244 {
245 actualTC->setCCReg(reg_idx, val);
246 checkerTC->setCCReg(reg_idx, val);
247 }
248
249 /** Reads this thread's PC state. */
250 TheISA::PCState pcState()
251 { return actualTC->pcState(); }
252
253 /** Sets this thread's PC state. */
254 void pcState(const TheISA::PCState &val)
255 {
256 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
257 val, checkerTC->pcState());
258 checkerTC->pcState(val);
259 checkerCPU->recordPCChange(val);
260 return actualTC->pcState(val);
261 }
262
263 void pcStateNoRecord(const TheISA::PCState &val)
264 {
265 return actualTC->pcState(val);
266 }
267
268 /** Reads this thread's PC. */
269 Addr instAddr()
270 { return actualTC->instAddr(); }
271
272 /** Reads this thread's next PC. */
273 Addr nextInstAddr()
274 { return actualTC->nextInstAddr(); }
275
276 /** Reads this thread's next PC. */
277 MicroPC microPC()
278 { return actualTC->microPC(); }
279
280 MiscReg readMiscRegNoEffect(int misc_reg)
281 { return actualTC->readMiscRegNoEffect(misc_reg); }
282
283 MiscReg readMiscReg(int misc_reg)
284 { return actualTC->readMiscReg(misc_reg); }
285
286 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
287 {
288 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
289 " and O3..\n", misc_reg);
290 checkerTC->setMiscRegNoEffect(misc_reg, val);
291 actualTC->setMiscRegNoEffect(misc_reg, val);
292 }
293
294 void setMiscReg(int misc_reg, const MiscReg &val)
295 {
296 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
297 " and O3..\n", misc_reg);
298 checkerTC->setMiscReg(misc_reg, val);
299 actualTC->setMiscReg(misc_reg, val);
300 }
301
302 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
303 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
304 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
305 int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
306
307 unsigned readStCondFailures()
308 { return actualTC->readStCondFailures(); }
309
310 void setStCondFailures(unsigned sc_failures)
311 {
312 actualTC->setStCondFailures(sc_failures);
313 }
314
315 // @todo: Fix this!
316 bool misspeculating() { return actualTC->misspeculating(); }
317
318 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
319
320 uint64_t readIntRegFlat(int idx)
321 { return actualTC->readIntRegFlat(idx); }
322
323 void setIntRegFlat(int idx, uint64_t val)
324 { actualTC->setIntRegFlat(idx, val); }
325
326 FloatReg readFloatRegFlat(int idx)
327 { return actualTC->readFloatRegFlat(idx); }
328
329 void setFloatRegFlat(int idx, FloatReg val)
330 { actualTC->setFloatRegFlat(idx, val); }
331
332 FloatRegBits readFloatRegBitsFlat(int idx)
333 { return actualTC->readFloatRegBitsFlat(idx); }
334
335 void setFloatRegBitsFlat(int idx, FloatRegBits val)
336 { actualTC->setFloatRegBitsFlat(idx, val); }
337
338 CCReg readCCRegFlat(int idx)
339 { return actualTC->readCCRegFlat(idx); }
340
341 void setCCRegFlat(int idx, CCReg val)
342 { actualTC->setCCRegFlat(idx, val); }
343};
344
345#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__