1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
32#define __CPU_CHECKER_THREAD_CONTEXT_HH__
33
34#include "arch/types.hh"
35#include "config/the_isa.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/simple_thread.hh"
38#include "cpu/thread_context.hh"
39
40class EndQuiesceEvent;
41namespace TheISA {
42 namespace Kernel {
43 class Statistics;
44 };
45};
46

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72 SimpleThread *checkerTC;
73 /** Pointer to the checker CPU. */
74 CheckerCPU *checkerCPU;
75
76 public:
77
78 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
79
80 void setCpuId(int id)
81 {
82 actualTC->setCpuId(id);
83 checkerTC->setCpuId(id);
84 }
85
86 int cpuId() { return actualTC->cpuId(); }
87
88 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
89
90 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
91
92#if FULL_SYSTEM
93 System *getSystemPtr() { return actualTC->getSystemPtr(); }
94
95 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
96
97 TheISA::Kernel::Statistics *getKernelStats()
98 { return actualTC->getKernelStats(); }
99
100 PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
101
102 FSTranslatingPortProxy* getVirtProxy()
103 { return actualTC->getVirtProxy(); }
104#else
105 SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
106
107 Process *getProcessPtr() { return actualTC->getProcessPtr(); }
108#endif
109
110 Status status() const { return actualTC->status(); }
111
112 void setStatus(Status new_status)
113 {
114 actualTC->setStatus(new_status);
115 checkerTC->setStatus(new_status);
116 }
117
118 /// Set the status to Active. Optional delay indicates number of
119 /// cycles to wait before beginning execution.
120 void activate(int delay = 1) { actualTC->activate(delay); }
121
122 /// Set the status to Suspended.
123 void suspend() { actualTC->suspend(); }
124
125 /// Set the status to Halted.
126 void halt() { actualTC->halt(); }
127
128#if FULL_SYSTEM
129 void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
130#endif
131
132 void takeOverFrom(ThreadContext *oldContext)
133 {
134 actualTC->takeOverFrom(oldContext);
135 checkerTC->copyState(oldContext);
136 }
137
138 void regStats(const std::string &name) { actualTC->regStats(name); }
139
140 void serialize(std::ostream &os) { actualTC->serialize(os); }
141 void unserialize(Checkpoint *cp, const std::string &section)
142 { actualTC->unserialize(cp, section); }
143
144#if FULL_SYSTEM
145 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
146
147 Tick readLastActivate() { return actualTC->readLastActivate(); }
148 Tick readLastSuspend() { return actualTC->readLastSuspend(); }
149
150 void profileClear() { return actualTC->profileClear(); }
151 void profileSample() { return actualTC->profileSample(); }
152#endif
153
154 int threadId() { return actualTC->threadId(); }
155
156 // @todo: Do I need this?
157 void copyArchRegs(ThreadContext *tc)
158 {
159 actualTC->copyArchRegs(tc);
160 checkerTC->copyArchRegs(tc);
161 }
162
163 void clearArchRegs()

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191 }
192
193 void setFloatRegBits(int reg_idx, FloatRegBits val)
194 {
195 actualTC->setFloatRegBits(reg_idx, val);
196 checkerTC->setFloatRegBits(reg_idx, val);
197 }
198
199 uint64_t readPC() { return actualTC->readPC(); }
200
201 void setPC(uint64_t val)
202 {
203 actualTC->setPC(val);
204 checkerTC->setPC(val);
205 checkerCPU->recordPCChange(val);
206 }
207
208 uint64_t readNextPC() { return actualTC->readNextPC(); }
209
210 void setNextPC(uint64_t val)
211 {
212 actualTC->setNextPC(val);
213 checkerTC->setNextPC(val);
214 checkerCPU->recordNextPCChange(val);
215 }
216
217 uint64_t readNextNPC() { return actualTC->readNextNPC(); }
218
219 void setNextNPC(uint64_t val)
220 {
221 actualTC->setNextNPC(val);
222 checkerTC->setNextNPC(val);
223 checkerCPU->recordNextPCChange(val);
224 }
225
226 MiscReg readMiscRegNoEffect(int misc_reg)
227 { return actualTC->readMiscRegNoEffect(misc_reg); }
228
229 MiscReg readMiscReg(int misc_reg)
230 { return actualTC->readMiscReg(misc_reg); }
231
232 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
233 {
234 checkerTC->setMiscRegNoEffect(misc_reg, val);
235 actualTC->setMiscRegNoEffect(misc_reg, val);
236 }
237
238 void setMiscReg(int misc_reg, const MiscReg &val)
239 {
240 checkerTC->setMiscReg(misc_reg, val);
241 actualTC->setMiscReg(misc_reg, val);
242 }
243
244 unsigned readStCondFailures()
245 { return actualTC->readStCondFailures(); }
246
247 void setStCondFailures(unsigned sc_failures)
248 {
249 checkerTC->setStCondFailures(sc_failures);
250 actualTC->setStCondFailures(sc_failures);
251 }
252
253 // @todo: Fix this!
254 bool misspeculating() { return actualTC->misspeculating(); }
255
256#if !FULL_SYSTEM
257 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
258#endif
259};
260
261#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__