1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
209 uint64_t readIntReg(int reg_idx)
210 { return actualTC->readIntReg(reg_idx); }
211
212 FloatRegBits readFloatRegBits(int reg_idx)
213 { return actualTC->readFloatRegBits(reg_idx); }
214
215 const VecRegContainer& readVecReg(const RegId& reg) const
216 { return actualTC->readVecReg(reg); }
217
218 /**
219 * Read vector register for modification, hierarchical indexing.
220 */
221 VecRegContainer& getWritableVecReg(const RegId& reg)

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259 /** @} */
260
261 const VecElem& readVecElem(const RegId& reg) const
262 { return actualTC->readVecElem(reg); }
263
264 CCReg readCCReg(int reg_idx)
265 { return actualTC->readCCReg(reg_idx); }
266
267 void setIntReg(int reg_idx, uint64_t val)
268 {
269 actualTC->setIntReg(reg_idx, val);
270 checkerTC->setIntReg(reg_idx, val);
271 }
272
273 void setFloatRegBits(int reg_idx, FloatRegBits val)
274 {
275 actualTC->setFloatRegBits(reg_idx, val);
276 checkerTC->setFloatRegBits(reg_idx, val);
277 }
278
279 void setVecReg(const RegId& reg, const VecRegContainer& val)
280 {
281 actualTC->setVecReg(reg, val);
282 checkerTC->setVecReg(reg, val);
283 }
284
285 void setVecElem(const RegId& reg, const VecElem& val)
286 {
287 actualTC->setVecElem(reg, val);
288 checkerTC->setVecElem(reg, val);
289 }
290
291 void setCCReg(int reg_idx, CCReg val)
292 {
293 actualTC->setCCReg(reg_idx, val);
294 checkerTC->setCCReg(reg_idx, val);
295 }
296
297 /** Reads this thread's PC state. */
298 TheISA::PCState pcState()
299 { return actualTC->pcState(); }
300
301 /** Sets this thread's PC state. */
302 void pcState(const TheISA::PCState &val)
303 {
304 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
305 val, checkerTC->pcState());
306 checkerTC->pcState(val);
307 checkerCPU->recordPCChange(val);
308 return actualTC->pcState(val);
309 }
310
311 void setNPC(Addr val)
312 {
313 checkerTC->setNPC(val);
314 actualTC->setNPC(val);
315 }
316
317 void pcStateNoRecord(const TheISA::PCState &val)
318 {
319 return actualTC->pcState(val);
320 }
321
322 /** Reads this thread's PC. */
323 Addr instAddr()
324 { return actualTC->instAddr(); }
325
326 /** Reads this thread's next PC. */
327 Addr nextInstAddr()
328 { return actualTC->nextInstAddr(); }
329
330 /** Reads this thread's next PC. */
331 MicroPC microPC()
332 { return actualTC->microPC(); }
333
334 MiscReg readMiscRegNoEffect(int misc_reg) const
335 { return actualTC->readMiscRegNoEffect(misc_reg); }
336
337 MiscReg readMiscReg(int misc_reg)
338 { return actualTC->readMiscReg(misc_reg); }
339
340 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
341 {
342 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
343 " and O3..\n", misc_reg);
344 checkerTC->setMiscRegNoEffect(misc_reg, val);
345 actualTC->setMiscRegNoEffect(misc_reg, val);
346 }
347
348 void setMiscReg(int misc_reg, const MiscReg &val)
349 {
350 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
351 " and O3..\n", misc_reg);
352 checkerTC->setMiscReg(misc_reg, val);
353 actualTC->setMiscReg(misc_reg, val);
354 }
355
356 RegId flattenRegId(const RegId& regId) const {
357 return actualTC->flattenRegId(regId);
358 }
359
360 unsigned readStCondFailures()
361 { return actualTC->readStCondFailures(); }
362
363 void setStCondFailures(unsigned sc_failures)
364 {
365 actualTC->setStCondFailures(sc_failures);
366 }
367
368 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
369
370 uint64_t readIntRegFlat(int idx)
371 { return actualTC->readIntRegFlat(idx); }
372
373 void setIntRegFlat(int idx, uint64_t val)
374 { actualTC->setIntRegFlat(idx, val); }
375
376 FloatRegBits readFloatRegBitsFlat(int idx)
377 { return actualTC->readFloatRegBitsFlat(idx); }
378
379 void setFloatRegBitsFlat(int idx, FloatRegBits val)
380 { actualTC->setFloatRegBitsFlat(idx, val); }
381
382 const VecRegContainer& readVecRegFlat(int idx) const
383 { return actualTC->readVecRegFlat(idx); }
384
385 /**
386 * Read vector register for modification, flat indexing.
387 */
388 VecRegContainer& getWritableVecRegFlat(int idx)
389 { return actualTC->getWritableVecRegFlat(idx); }
390
391 void setVecRegFlat(int idx, const VecRegContainer& val)
392 { actualTC->setVecRegFlat(idx, val); }
393
394 const VecElem& readVecElemFlat(const RegIndex& idx,
395 const ElemIndex& elem_idx) const
396 { return actualTC->readVecElemFlat(idx, elem_idx); }
397

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