1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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201 {
202 actualTC->clearArchRegs();
203 checkerTC->clearArchRegs();
204 }
205
206 //
207 // New accessors for new decoder.
208 //
209 RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
210
211 RegVal
212 readFloatRegBits(int reg_idx)
213 {
214 return actualTC->readFloatRegBits(reg_idx);
215 }
216
217 const VecRegContainer& readVecReg(const RegId& reg) const
218 { return actualTC->readVecReg(reg); }
219
220 /**
221 * Read vector register for modification, hierarchical indexing.
222 */
223 VecRegContainer& getWritableVecReg(const RegId& reg)

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261 /** @} */
262
263 const VecElem& readVecElem(const RegId& reg) const
264 { return actualTC->readVecElem(reg); }
265
266 CCReg readCCReg(int reg_idx)
267 { return actualTC->readCCReg(reg_idx); }
268
269 void
270 setIntReg(int reg_idx, RegVal val)
271 {
272 actualTC->setIntReg(reg_idx, val);
273 checkerTC->setIntReg(reg_idx, val);
274 }
275
276 void
277 setFloatRegBits(int reg_idx, RegVal val)
278 {
279 actualTC->setFloatRegBits(reg_idx, val);
280 checkerTC->setFloatRegBits(reg_idx, val);
281 }
282
283 void
284 setVecReg(const RegId& reg, const VecRegContainer& val)
285 {
286 actualTC->setVecReg(reg, val);
287 checkerTC->setVecReg(reg, val);
288 }
289
290 void
291 setVecElem(const RegId& reg, const VecElem& val)
292 {
293 actualTC->setVecElem(reg, val);
294 checkerTC->setVecElem(reg, val);
295 }
296
297 void
298 setCCReg(int reg_idx, CCReg val)
299 {
300 actualTC->setCCReg(reg_idx, val);
301 checkerTC->setCCReg(reg_idx, val);
302 }
303
304 /** Reads this thread's PC state. */
305 TheISA::PCState pcState()
306 { return actualTC->pcState(); }
307
308 /** Sets this thread's PC state. */
309 void
310 pcState(const TheISA::PCState &val)
311 {
312 DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
313 val, checkerTC->pcState());
314 checkerTC->pcState(val);
315 checkerCPU->recordPCChange(val);
316 return actualTC->pcState(val);
317 }
318
319 void
320 setNPC(Addr val)
321 {
322 checkerTC->setNPC(val);
323 actualTC->setNPC(val);
324 }
325
326 void
327 pcStateNoRecord(const TheISA::PCState &val)
328 {
329 return actualTC->pcState(val);
330 }
331
332 /** Reads this thread's PC. */
333 Addr instAddr()
334 { return actualTC->instAddr(); }
335
336 /** Reads this thread's next PC. */
337 Addr nextInstAddr()
338 { return actualTC->nextInstAddr(); }
339
340 /** Reads this thread's next PC. */
341 MicroPC microPC()
342 { return actualTC->microPC(); }
343
344 RegVal readMiscRegNoEffect(int misc_reg) const
345 { return actualTC->readMiscRegNoEffect(misc_reg); }
346
347 RegVal readMiscReg(int misc_reg)
348 { return actualTC->readMiscReg(misc_reg); }
349
350 void
351 setMiscRegNoEffect(int misc_reg, const RegVal &val)
352 {
353 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
354 " and O3..\n", misc_reg);
355 checkerTC->setMiscRegNoEffect(misc_reg, val);
356 actualTC->setMiscRegNoEffect(misc_reg, val);
357 }
358
359 void
360 setMiscReg(int misc_reg, const RegVal &val)
361 {
362 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
363 " and O3..\n", misc_reg);
364 checkerTC->setMiscReg(misc_reg, val);
365 actualTC->setMiscReg(misc_reg, val);
366 }
367
368 RegId
369 flattenRegId(const RegId& regId) const
370 {
371 return actualTC->flattenRegId(regId);
372 }
373
374 unsigned readStCondFailures()
375 { return actualTC->readStCondFailures(); }
376
377 void
378 setStCondFailures(unsigned sc_failures)
379 {
380 actualTC->setStCondFailures(sc_failures);
381 }
382
383 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
384
385 RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
386
387 void
388 setIntRegFlat(int idx, RegVal val)
389 {
390 actualTC->setIntRegFlat(idx, val);
391 }
392
393 RegVal
394 readFloatRegBitsFlat(int idx)
395 {
396 return actualTC->readFloatRegBitsFlat(idx);
397 }
398
399 void
400 setFloatRegBitsFlat(int idx, RegVal val)
401 {
402 actualTC->setFloatRegBitsFlat(idx, val);
403 }
404
405 const VecRegContainer &
406 readVecRegFlat(int idx) const
407 {
408 return actualTC->readVecRegFlat(idx);
409 }
410
411 /**
412 * Read vector register for modification, flat indexing.
413 */
414 VecRegContainer &
415 getWritableVecRegFlat(int idx)
416 {
417 return actualTC->getWritableVecRegFlat(idx);
418 }
419
420 void setVecRegFlat(int idx, const VecRegContainer& val)
421 { actualTC->setVecRegFlat(idx, val); }
422
423 const VecElem& readVecElemFlat(const RegIndex& idx,
424 const ElemIndex& elem_idx) const
425 { return actualTC->readVecElemFlat(idx, elem_idx); }
426

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