cpu.hh (9176:6807aa361e80) cpu.hh (9608:e2b6b86fda03)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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99 virtual void init();
100
101 typedef CheckerCPUParams Params;
102 CheckerCPU(Params *p);
103 virtual ~CheckerCPU();
104
105 void setSystem(System *system);
106
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 90 unchanged lines hidden (view full) ---

99 virtual void init();
100
101 typedef CheckerCPUParams Params;
102 CheckerCPU(Params *p);
103 virtual ~CheckerCPU();
104
105 void setSystem(System *system);
106
107 void setIcachePort(CpuPort *icache_port);
107 void setIcachePort(MasterPort *icache_port);
108
108
109 void setDcachePort(CpuPort *dcache_port);
109 void setDcachePort(MasterPort *dcache_port);
110
110
111 CpuPort &getDataPort()
111 MasterPort &getDataPort()
112 {
113 // the checker does not have ports on its own so return the
114 // data port of the actual CPU core
115 assert(dcachePort);
116 return *dcachePort;
117 }
118
112 {
113 // the checker does not have ports on its own so return the
114 // data port of the actual CPU core
115 assert(dcachePort);
116 return *dcachePort;
117 }
118
119 CpuPort &getInstPort()
119 MasterPort &getInstPort()
120 {
121 // the checker does not have ports on its own so return the
122 // data port of the actual CPU core
123 assert(icachePort);
124 return *icachePort;
125 }
126
127 protected:
128
129 std::vector<Process*> workload;
130
131 System *systemPtr;
132
120 {
121 // the checker does not have ports on its own so return the
122 // data port of the actual CPU core
123 assert(icachePort);
124 return *icachePort;
125 }
126
127 protected:
128
129 std::vector<Process*> workload;
130
131 System *systemPtr;
132
133 CpuPort *icachePort;
134 CpuPort *dcachePort;
133 MasterPort *icachePort;
134 MasterPort *dcachePort;
135
136 ThreadContext *tc;
137
138 TheISA::TLB *itb;
139 TheISA::TLB *dtb;
140
141 Addr dbg_vtophys(Addr addr);
142

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136 ThreadContext *tc;
137
138 TheISA::TLB *itb;
139 TheISA::TLB *dtb;
140
141 Addr dbg_vtophys(Addr addr);
142

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