cpu.hh (8809:bb10807da889) cpu.hh (8832:247fee427324)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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88 */
89class CheckerCPU : public BaseCPU
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 79 unchanged lines hidden (view full) ---

88 */
89class CheckerCPU : public BaseCPU
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
96
97 /** id attached to all issued requests */
98 MasterID masterId;
96 public:
97 virtual void init();
98
99 public:
100 typedef CheckerCPUParams Params;
101 const Params *params() const
102 { return reinterpret_cast<const Params *>(_params); }
103 CheckerCPU(Params *p);

--- 313 unchanged lines hidden --- 		99 public:
100 virtual void init();
101
102 public:
103 typedef CheckerCPUParams Params;
104 const Params *params() const
105 { return reinterpret_cast<const Params *>(_params); }
106 CheckerCPU(Params *p);

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