cpu.hh (5358:e9acb84bbafb) | cpu.hh (5529:9ae69b9cd7fd) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 51 unchanged lines hidden (view full) --- 60 61#else 62 63class Process; 64 65#endif // FULL_SYSTEM 66template <class> 67class BaseDynInst; | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 51 unchanged lines hidden (view full) --- 60 61#else 62 63class Process; 64 65#endif // FULL_SYSTEM 66template <class> 67class BaseDynInst; |
68class CheckerCPUParams; |
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68class ThreadContext; 69class MemInterface; 70class Checkpoint; 71class Request; 72 73/** 74 * CheckerCPU class. Dynamically verifies instructions as they are 75 * completed by making sure that the instruction and its results match --- 15 unchanged lines hidden (view full) --- 91 protected: 92 typedef TheISA::MachInst MachInst; 93 typedef TheISA::FloatReg FloatReg; 94 typedef TheISA::FloatRegBits FloatRegBits; 95 typedef TheISA::MiscReg MiscReg; 96 public: 97 virtual void init(); 98 | 69class ThreadContext; 70class MemInterface; 71class Checkpoint; 72class Request; 73 74/** 75 * CheckerCPU class. Dynamically verifies instructions as they are 76 * completed by making sure that the instruction and its results match --- 15 unchanged lines hidden (view full) --- 92 protected: 93 typedef TheISA::MachInst MachInst; 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 typedef TheISA::MiscReg MiscReg; 97 public: 98 virtual void init(); 99 |
99 struct Params : public BaseCPU::Params 100 { 101#if FULL_SYSTEM 102 TheISA::ITB *itb; 103 TheISA::DTB *dtb; 104#else 105 Process *process; 106#endif 107 bool exitOnError; 108 bool updateOnError; 109 bool warnOnlyOnLoadError; 110 }; 111 | |
112 public: | 100 public: |
101 typedef CheckerCPUParams Params; 102 const Params *params() const 103 { return reinterpret_cast<const Params *>(_params); } |
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113 CheckerCPU(Params *p); 114 virtual ~CheckerCPU(); 115 116 Process *process; 117 118 void setSystem(System *system); 119 120 System *systemPtr; --- 311 unchanged lines hidden --- | 104 CheckerCPU(Params *p); 105 virtual ~CheckerCPU(); 106 107 Process *process; 108 109 void setSystem(System *system); 110 111 System *systemPtr; --- 311 unchanged lines hidden --- |