cpu.hh (3735:86a7cf4dcc11) cpu.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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293 uint64_t readPC() { return thread->readPC(); }
294
295 uint64_t readNextPC() { return thread->readNextPC(); }
296
297 void setNextPC(uint64_t val) {
298 thread->setNextPC(val);
299 }
300
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 284 unchanged lines hidden (view full) ---

293 uint64_t readPC() { return thread->readPC(); }
294
295 uint64_t readNextPC() { return thread->readNextPC(); }
296
297 void setNextPC(uint64_t val) {
298 thread->setNextPC(val);
299 }
300
301 MiscReg readMiscReg(int misc_reg)
301 MiscReg readMiscRegNoEffect(int misc_reg)
302 {
302 {
303 return thread->readMiscReg(misc_reg);
303 return thread->readMiscRegNoEffect(misc_reg);
304 }
305
304 }
305
306 MiscReg readMiscRegWithEffect(int misc_reg)
306 MiscReg readMiscReg(int misc_reg)
307 {
307 {
308 return thread->readMiscRegWithEffect(misc_reg);
308 return thread->readMiscReg(misc_reg);
309 }
310
309 }
310
311 void setMiscReg(int misc_reg, const MiscReg &val)
311 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
312 {
313 result.integer = val;
314 miscRegIdxs.push(misc_reg);
312 {
313 result.integer = val;
314 miscRegIdxs.push(misc_reg);
315 return thread->setMiscReg(misc_reg, val);
315 return thread->setMiscRegNoEffect(misc_reg, val);
316 }
317
316 }
317
318 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
318 void setMiscReg(int misc_reg, const MiscReg &val)
319 {
320 miscRegIdxs.push(misc_reg);
319 {
320 miscRegIdxs.push(misc_reg);
321 return thread->setMiscRegWithEffect(misc_reg, val);
321 return thread->setMiscReg(misc_reg, val);
322 }
323
324 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
325 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
326
327 bool translateInstReq(Request *req);
328 void translateDataWriteReq(Request *req);
329 void translateDataReadReq(Request *req);

--- 86 unchanged lines hidden --- 		322 }
323
324 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
325 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
326
327 bool translateInstReq(Request *req);
328 void translateDataWriteReq(Request *req);
329 void translateDataReadReq(Request *req);

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