cpu.hh (3521:0b0b3551def0) cpu.hh (3735:86a7cf4dcc11)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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211 // renaming. We find the architectural register index by indexing
212 // into the instruction's own operand index table. Note that a
213 // raw pointer to the StaticInst is provided instead of a
214 // ref-counted StaticInstPtr to redice overhead. This is fine as
215 // long as these methods don't copy the pointer into any long-term
216 // storage (which is pretty hard to imagine they would have reason
217 // to do).
218
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 202 unchanged lines hidden (view full) ---

211 // renaming. We find the architectural register index by indexing
212 // into the instruction's own operand index table. Note that a
213 // raw pointer to the StaticInst is provided instead of a
214 // ref-counted StaticInstPtr to redice overhead. This is fine as
215 // long as these methods don't copy the pointer into any long-term
216 // storage (which is pretty hard to imagine they would have reason
217 // to do).
218
219 uint64_t readIntReg(const StaticInst *si, int idx)
219 uint64_t readIntRegOperand(const StaticInst *si, int idx)
220 {
221 return thread->readIntReg(si->srcRegIdx(idx));
222 }
223
220 {
221 return thread->readIntReg(si->srcRegIdx(idx));
222 }
223
224 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
224 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
225 {
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx, width);
228 }
229
225 {
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx, width);
228 }
229
230 FloatReg readFloatReg(const StaticInst *si, int idx)
230 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
231 {
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatReg(reg_idx);
234 }
235
231 {
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatReg(reg_idx);
234 }
235
236 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
236 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
237 int width)
237 {
238 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
239 return thread->readFloatRegBits(reg_idx, width);
240 }
241
238 {
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return thread->readFloatRegBits(reg_idx, width);
241 }
242
242 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
243 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
243 {
244 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
245 return thread->readFloatRegBits(reg_idx);
246 }
247
244 {
245 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
246 return thread->readFloatRegBits(reg_idx);
247 }
248
248 void setIntReg(const StaticInst *si, int idx, uint64_t val)
249 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
249 {
250 thread->setIntReg(si->destRegIdx(idx), val);
251 result.integer = val;
252 }
253
250 {
251 thread->setIntReg(si->destRegIdx(idx), val);
252 result.integer = val;
253 }
254
254 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
255 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
256 int width)
255 {
256 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
257 thread->setFloatReg(reg_idx, val, width);
258 switch(width) {
259 case 32:
260 result.dbl = (double)val;
261 break;
262 case 64:
263 result.dbl = val;
264 break;
265 };
266 }
267
257 {
258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
259 thread->setFloatReg(reg_idx, val, width);
260 switch(width) {
261 case 32:
262 result.dbl = (double)val;
263 break;
264 case 64:
265 result.dbl = val;
266 break;
267 };
268 }
269
268 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
270 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
269 {
270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
271 thread->setFloatReg(reg_idx, val);
272 result.dbl = (double)val;
273 }
274
271 {
272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
273 thread->setFloatReg(reg_idx, val);
274 result.dbl = (double)val;
275 }
276
275 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
276 int width)
277 void setFloatRegOperandBits(const StaticInst *si, int idx,
278 FloatRegBits val, int width)
277 {
278 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
279 thread->setFloatRegBits(reg_idx, val, width);
280 result.integer = val;
281 }
282
279 {
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
281 thread->setFloatRegBits(reg_idx, val, width);
282 result.integer = val;
283 }
284
283 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
285 void setFloatRegOperandBits(const StaticInst *si, int idx,
286 FloatRegBits val)
284 {
285 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
286 thread->setFloatRegBits(reg_idx, val);
287 result.integer = val;
288 }
289
290 uint64_t readPC() { return thread->readPC(); }
291

--- 121 unchanged lines hidden --- 		287 {
288 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
289 thread->setFloatRegBits(reg_idx, val);
290 result.integer = val;
291 }
292
293 uint64_t readPC() { return thread->readPC(); }
294

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