cpu.hh (3454:26850ac19a39) cpu.hh (3468:cf23ad1ceef2)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50namespace TheISA
51{
52 class ITB;
53 class DTB;
54}
50class Processor;
55class Processor;
51class AlphaITB;
52class AlphaDTB;
53class PhysicalMemory;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;

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91 typedef TheISA::FloatRegBits FloatRegBits;
92 typedef TheISA::MiscReg MiscReg;
93 public:
94 virtual void init();
95
96 struct Params : public BaseCPU::Params
97 {
98#if FULL_SYSTEM
56class PhysicalMemory;
57
58class RemoteGDB;
59class GDBListener;
60
61#else
62
63class Process;

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94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
96 public:
97 virtual void init();
98
99 struct Params : public BaseCPU::Params
100 {
101#if FULL_SYSTEM
99 AlphaITB *itb;
100 AlphaDTB *dtb;
102 TheISA::ITB *itb;
103 TheISA::DTB *dtb;
101#else
102 Process *process;
103#endif
104 bool exitOnError;
105 bool updateOnError;
106 bool warnOnlyOnLoadError;
107 };
108

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135 }
136
137 public:
138 // Primary thread being run.
139 SimpleThread *thread;
140
141 ThreadContext *tc;
142
104#else
105 Process *process;
106#endif
107 bool exitOnError;
108 bool updateOnError;
109 bool warnOnlyOnLoadError;
110 };
111

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138 }
139
140 public:
141 // Primary thread being run.
142 SimpleThread *thread;
143
144 ThreadContext *tc;
145
143 AlphaITB *itb;
144 AlphaDTB *dtb;
146 TheISA::ITB *itb;
147 TheISA::DTB *dtb;
145
146#if FULL_SYSTEM
147 Addr dbg_vtophys(Addr addr);
148#endif
149
150 union Result {
151 uint64_t integer;
152// float fp;

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296 thread->setNextPC(val);
297 }
298
299 MiscReg readMiscReg(int misc_reg)
300 {
301 return thread->readMiscReg(misc_reg);
302 }
303
148
149#if FULL_SYSTEM
150 Addr dbg_vtophys(Addr addr);
151#endif
152
153 union Result {
154 uint64_t integer;
155// float fp;

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299 thread->setNextPC(val);
300 }
301
302 MiscReg readMiscReg(int misc_reg)
303 {
304 return thread->readMiscReg(misc_reg);
305 }
306
304 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
307 MiscReg readMiscRegWithEffect(int misc_reg)
305 {
308 {
306 return thread->readMiscRegWithEffect(misc_reg, fault);
309 return thread->readMiscRegWithEffect(misc_reg);
307 }
308
310 }
311
309 Fault setMiscReg(int misc_reg, const MiscReg &val)
312 void setMiscReg(int misc_reg, const MiscReg &val)
310 {
311 result.integer = val;
312 miscRegIdxs.push(misc_reg);
313 return thread->setMiscReg(misc_reg, val);
314 }
315
313 {
314 result.integer = val;
315 miscRegIdxs.push(misc_reg);
316 return thread->setMiscReg(misc_reg, val);
317 }
318
316 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
319 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
317 {
318 miscRegIdxs.push(misc_reg);
319 return thread->setMiscRegWithEffect(misc_reg, val);
320 }
321
322 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
323 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
324

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321 miscRegIdxs.push(misc_reg);
322 return thread->setMiscRegWithEffect(misc_reg, val);
323 }
324
325 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
326 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
327

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