cpu.hh (3125:febd811bccc6) cpu.hh (3126:756092c6383c)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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253 }
254
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
258 thread->setFloatReg(reg_idx, val, width);
259 switch(width) {
260 case 32:
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 244 unchanged lines hidden (view full) ---

253 }
254
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
258 thread->setFloatReg(reg_idx, val, width);
259 switch(width) {
260 case 32:
261 result.fp = val;
261 result.dbl = (double)val;
262 break;
263 case 64:
264 result.dbl = val;
265 break;
266 };
267 }
268
269 void setFloatReg(const StaticInst *si, int idx, FloatReg val)

--- 147 unchanged lines hidden --- 		262 break;
263 case 64:
264 result.dbl = val;
265 break;
266 };
267 }
268
269 void setFloatReg(const StaticInst *si, int idx, FloatReg val)

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