cpu.hh (2930:51a61690c402) | cpu.hh (3125:febd811bccc6) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 88 unchanged lines hidden (view full) --- 97 { 98#if FULL_SYSTEM 99 AlphaITB *itb; 100 AlphaDTB *dtb; 101#else 102 Process *process; 103#endif 104 bool exitOnError; | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 88 unchanged lines hidden (view full) --- 97 { 98#if FULL_SYSTEM 99 AlphaITB *itb; 100 AlphaDTB *dtb; 101#else 102 Process *process; 103#endif 104 bool exitOnError; |
105 bool updateOnError; |
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105 bool warnOnlyOnLoadError; 106 }; 107 108 public: 109 CheckerCPU(Params *p); 110 virtual ~CheckerCPU(); 111 112 Process *process; --- 30 unchanged lines hidden (view full) --- 143 AlphaDTB *dtb; 144 145#if FULL_SYSTEM 146 Addr dbg_vtophys(Addr addr); 147#endif 148 149 union Result { 150 uint64_t integer; | 106 bool warnOnlyOnLoadError; 107 }; 108 109 public: 110 CheckerCPU(Params *p); 111 virtual ~CheckerCPU(); 112 113 Process *process; --- 30 unchanged lines hidden (view full) --- 144 AlphaDTB *dtb; 145 146#if FULL_SYSTEM 147 Addr dbg_vtophys(Addr addr); 148#endif 149 150 union Result { 151 uint64_t integer; |
151 float fp; | 152// float fp; |
152 double dbl; 153 }; 154 155 Result result; 156 157 // current instruction 158 MachInst machInst; 159 --- 104 unchanged lines hidden (view full) --- 264 break; 265 }; 266 } 267 268 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 269 { 270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 271 thread->setFloatReg(reg_idx, val); | 153 double dbl; 154 }; 155 156 Result result; 157 158 // current instruction 159 MachInst machInst; 160 --- 104 unchanged lines hidden (view full) --- 265 break; 266 }; 267 } 268 269 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 270 { 271 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 272 thread->setFloatReg(reg_idx, val); |
272 result.fp = val; | 273 result.dbl = (double)val; |
273 } 274 275 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, 276 int width) 277 { 278 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 279 thread->setFloatRegBits(reg_idx, val, width); 280 result.integer = val; --- 32 unchanged lines hidden (view full) --- 313 } 314 315 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 316 { 317 miscRegIdxs.push(misc_reg); 318 return thread->setMiscRegWithEffect(misc_reg, val); 319 } 320 | 274 } 275 276 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, 277 int width) 278 { 279 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 280 thread->setFloatRegBits(reg_idx, val, width); 281 result.integer = val; --- 32 unchanged lines hidden (view full) --- 314 } 315 316 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 317 { 318 miscRegIdxs.push(misc_reg); 319 return thread->setMiscRegWithEffect(misc_reg, val); 320 } 321 |
321 void recordPCChange(uint64_t val) { changedPC = true; } | 322 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } |
322 void recordNextPCChange(uint64_t val) { changedNextPC = true; } 323 324 bool translateInstReq(Request *req); 325 void translateDataWriteReq(Request *req); 326 void translateDataReadReq(Request *req); 327 328#if FULL_SYSTEM 329 Fault hwrei() { return thread->hwrei(); } --- 25 unchanged lines hidden (view full) --- 355 Request *unverifiedReq; 356 uint8_t *unverifiedMemData; 357 358 bool changedPC; 359 bool willChangePC; 360 uint64_t newPC; 361 bool changedNextPC; 362 bool exitOnError; | 323 void recordNextPCChange(uint64_t val) { changedNextPC = true; } 324 325 bool translateInstReq(Request *req); 326 void translateDataWriteReq(Request *req); 327 void translateDataReadReq(Request *req); 328 329#if FULL_SYSTEM 330 Fault hwrei() { return thread->hwrei(); } --- 25 unchanged lines hidden (view full) --- 356 Request *unverifiedReq; 357 uint8_t *unverifiedMemData; 358 359 bool changedPC; 360 bool willChangePC; 361 uint64_t newPC; 362 bool changedNextPC; 363 bool exitOnError; |
364 bool updateOnError; |
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363 bool warnOnlyOnLoadError; 364 365 InstSeqNum youngestSN; 366}; 367 368/** 369 * Templated Checker class. This Checker class is templated on the 370 * DynInstPtr of the instruction type that will be verified. Proper 371 * template instantiations of the Checker must be placed at the bottom 372 * of checker/cpu.cc. 373 */ 374template <class DynInstPtr> 375class Checker : public CheckerCPU 376{ 377 public: 378 Checker(Params *p) | 365 bool warnOnlyOnLoadError; 366 367 InstSeqNum youngestSN; 368}; 369 370/** 371 * Templated Checker class. This Checker class is templated on the 372 * DynInstPtr of the instruction type that will be verified. Proper 373 * template instantiations of the Checker must be placed at the bottom 374 * of checker/cpu.cc. 375 */ 376template <class DynInstPtr> 377class Checker : public CheckerCPU 378{ 379 public: 380 Checker(Params *p) |
379 : CheckerCPU(p) | 381 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) |
380 { } 381 382 void switchOut(); 383 void takeOverFrom(BaseCPU *oldCPU); 384 385 void verify(DynInstPtr &inst); 386 387 void validateInst(DynInstPtr &inst); 388 void validateExecution(DynInstPtr &inst); 389 void validateState(); 390 391 void copyResult(DynInstPtr &inst); 392 393 private: 394 void handleError(DynInstPtr &inst) 395 { | 382 { } 383 384 void switchOut(); 385 void takeOverFrom(BaseCPU *oldCPU); 386 387 void verify(DynInstPtr &inst); 388 389 void validateInst(DynInstPtr &inst); 390 void validateExecution(DynInstPtr &inst); 391 void validateState(); 392 393 void copyResult(DynInstPtr &inst); 394 395 private: 396 void handleError(DynInstPtr &inst) 397 { |
396 if (exitOnError) | 398 if (exitOnError) { |
397 dumpAndExit(inst); | 399 dumpAndExit(inst); |
400 } else if (updateOnError) { 401 updateThisCycle = true; 402 } |
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398 } 399 400 void dumpAndExit(DynInstPtr &inst); 401 | 403 } 404 405 void dumpAndExit(DynInstPtr &inst); 406 |
407 bool updateThisCycle; 408 409 DynInstPtr unverifiedInst; 410 |
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402 std::list<DynInstPtr> instList; 403 typedef typename std::list<DynInstPtr>::iterator InstListIt; 404 void dumpInsts(); 405}; 406 407#endif // __CPU_CHECKER_CPU_HH__ | 411 std::list<DynInstPtr> instList; 412 typedef typename std::list<DynInstPtr>::iterator InstListIt; 413 void dumpInsts(); 414}; 415 416#endif // __CPU_CHECKER_CPU_HH__ |