cpu.hh (2871:7ed5c9ef3eb6) cpu.hh (2930:51a61690c402)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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165 // number of simulated instructions
166 Counter numInst;
167 Counter startNumInst;
168
169 std::queue<int> miscRegIdxs;
170
171 virtual Counter totalInstructions() const
172 {
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 156 unchanged lines hidden (view full) ---

165 // number of simulated instructions
166 Counter numInst;
167 Counter startNumInst;
168
169 std::queue<int> miscRegIdxs;
170
171 virtual Counter totalInstructions() const
172 {
173 return numInst - startNumInst;
173 return 0;
174 }
175
176 // number of simulated loads
177 Counter numLoad;
178 Counter startNumLoad;
179
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string &section);

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175
176 // number of simulated loads
177 Counter numLoad;
178 Counter startNumLoad;
179
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string &section);

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