cpu.hh (2689:dbf969c18a65) cpu.hh (2690:f4337c0d9e6f)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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94 public:
95 virtual void init();
96
97 struct Params : public BaseCPU::Params
98 {
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 85 unchanged lines hidden (view full) ---

94 public:
95 virtual void init();
96
97 struct Params : public BaseCPU::Params
98 {
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
102 FunctionalMemory *mem;
103#else
104 Process *process;
105#endif
106 bool exitOnError;
107 };
108
109 public:
110 CheckerCPU(Params *p);
111 virtual ~CheckerCPU();
112
113 Process *process;
114
115 void setMemory(MemObject *mem);
116
117 MemObject *memPtr;
118
102#else
103 Process *process;
104#endif
105 bool exitOnError;
106 };
107
108 public:
109 CheckerCPU(Params *p);
110 virtual ~CheckerCPU();
111
112 Process *process;
113
114 void setMemory(MemObject *mem);
115
116 MemObject *memPtr;
117
119#if FULL_SYSTEM
120 void setSystem(System *system);
121
122 System *systemPtr;
118 void setSystem(System *system);
119
120 System *systemPtr;
123#endif
124
125 void setIcachePort(Port *icache_port);
126
127 Port *icachePort;
128
129 void setDcachePort(Port *dcache_port);
130
131 Port *dcachePort;

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322 void translateDataWriteReq(Request *req);
323 void translateDataReadReq(Request *req);
324
325#if FULL_SYSTEM
326 Fault hwrei() { return thread->hwrei(); }
327 int readIntrFlag() { return thread->readIntrFlag(); }
328 void setIntrFlag(int val) { thread->setIntrFlag(val); }
329 bool inPalMode() { return thread->inPalMode(); }
121
122 void setIcachePort(Port *icache_port);
123
124 Port *icachePort;
125
126 void setDcachePort(Port *dcache_port);
127
128 Port *dcachePort;

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319 void translateDataWriteReq(Request *req);
320 void translateDataReadReq(Request *req);
321
322#if FULL_SYSTEM
323 Fault hwrei() { return thread->hwrei(); }
324 int readIntrFlag() { return thread->readIntrFlag(); }
325 void setIntrFlag(int val) { thread->setIntrFlag(val); }
326 bool inPalMode() { return thread->inPalMode(); }
330 void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
327 void ev5_trap(Fault fault) { fault->invoke(tc); }
331 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
332#else
333 // Assume that the normal CPU's call to syscall was successful.
334 // The checker's state would have already been updated by the syscall.
335 void syscall(uint64_t callnum) { }
336#endif
337
338 void handleError()

--- 51 unchanged lines hidden --- 		328 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
329#else
330 // Assume that the normal CPU's call to syscall was successful.
331 // The checker's state would have already been updated by the syscall.
332 void syscall(uint64_t callnum) { }
333#endif
334
335 void handleError()

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