cpu.hh (2680:246e7104f744) cpu.hh (2683:d6b72bb2ed97)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include <queue>
34#include <map>
35
36#include "arch/types.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/base_dyn_inst.hh"
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include <queue>
34#include <map>
35
36#include "arch/types.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/base_dyn_inst.hh"
41#include "cpu/cpu_exec_context.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/pc_event.hh"
43#include "cpu/static_inst.hh"
44#include "sim/eventq.hh"
45
46// forward declarations
47#if FULL_SYSTEM
48class Processor;
49class AlphaITB;

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72 * the independent execution of the benchmark inside the checker. The
73 * checker verifies instructions in order, regardless of the order in
74 * which instructions complete. There are certain results that can
75 * not be verified, specifically the result of a store conditional or
76 * the values of uncached accesses. In these cases, and with
77 * instructions marked as "IsUnverifiable", the checker assumes that
78 * the value from the main CPU's execution is correct and simply
79 * copies that value. It provides a CheckerThreadContext (see
42#include "cpu/pc_event.hh"
43#include "cpu/static_inst.hh"
44#include "sim/eventq.hh"
45
46// forward declarations
47#if FULL_SYSTEM
48class Processor;
49class AlphaITB;

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72 * the independent execution of the benchmark inside the checker. The
73 * checker verifies instructions in order, regardless of the order in
74 * which instructions complete. There are certain results that can
75 * not be verified, specifically the result of a store conditional or
76 * the values of uncached accesses. In these cases, and with
77 * instructions marked as "IsUnverifiable", the checker assumes that
78 * the value from the main CPU's execution is correct and simply
79 * copies that value. It provides a CheckerThreadContext (see
80 * checker/exec_context.hh) that provides hooks for updating the
80 * checker/thread_context.hh) that provides hooks for updating the
81 * Checker's state through any ThreadContext accesses. This allows the
82 * checker to be able to correctly verify instructions, even with
83 * external accesses to the ThreadContext that change state.
84 */
85class CheckerCPU : public BaseCPU
86{
87 protected:
88 typedef TheISA::MachInst MachInst;

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124
125 Port *icachePort;
126
127 void setDcachePort(Port *dcache_port);
128
129 Port *dcachePort;
130
131 public:
81 * Checker's state through any ThreadContext accesses. This allows the
82 * checker to be able to correctly verify instructions, even with
83 * external accesses to the ThreadContext that change state.
84 */
85class CheckerCPU : public BaseCPU
86{
87 protected:
88 typedef TheISA::MachInst MachInst;

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124
125 Port *icachePort;
126
127 void setDcachePort(Port *dcache_port);
128
129 Port *dcachePort;
130
131 public:
132 // execution context
133 CPUExecContext *cpuXC;
132 // Primary thread being run.
133 SimpleThread *thread;
134
135 ThreadContext *tc;
136
137 AlphaITB *itb;
138 AlphaDTB *dtb;
139
140#if FULL_SYSTEM
141 Addr dbg_vtophys(Addr addr);

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208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 uint64_t readIntReg(const StaticInst *si, int idx)
215 {
134
135 ThreadContext *tc;
136
137 AlphaITB *itb;
138 AlphaDTB *dtb;
139
140#if FULL_SYSTEM
141 Addr dbg_vtophys(Addr addr);

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208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 uint64_t readIntReg(const StaticInst *si, int idx)
215 {
216 return cpuXC->readIntReg(si->srcRegIdx(idx));
216 return thread->readIntReg(si->srcRegIdx(idx));
217 }
218
219 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
220 {
221 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
217 }
218
219 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
220 {
221 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
222 return cpuXC->readFloatReg(reg_idx, width);
222 return thread->readFloatReg(reg_idx, width);
223 }
224
225 FloatReg readFloatReg(const StaticInst *si, int idx)
226 {
227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
223 }
224
225 FloatReg readFloatReg(const StaticInst *si, int idx)
226 {
227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
228 return cpuXC->readFloatReg(reg_idx);
228 return thread->readFloatReg(reg_idx);
229 }
230
231 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
232 {
233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
229 }
230
231 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
232 {
233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
234 return cpuXC->readFloatRegBits(reg_idx, width);
234 return thread->readFloatRegBits(reg_idx, width);
235 }
236
237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
238 {
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
235 }
236
237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
238 {
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return cpuXC->readFloatRegBits(reg_idx);
240 return thread->readFloatRegBits(reg_idx);
241 }
242
243 void setIntReg(const StaticInst *si, int idx, uint64_t val)
244 {
241 }
242
243 void setIntReg(const StaticInst *si, int idx, uint64_t val)
244 {
245 cpuXC->setIntReg(si->destRegIdx(idx), val);
245 thread->setIntReg(si->destRegIdx(idx), val);
246 result.integer = val;
247 }
248
249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
250 {
251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
246 result.integer = val;
247 }
248
249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
250 {
251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
252 cpuXC->setFloatReg(reg_idx, val, width);
252 thread->setFloatReg(reg_idx, val, width);
253 switch(width) {
254 case 32:
255 result.fp = val;
256 break;
257 case 64:
258 result.dbl = val;
259 break;
260 };
261 }
262
263 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
253 switch(width) {
254 case 32:
255 result.fp = val;
256 break;
257 case 64:
258 result.dbl = val;
259 break;
260 };
261 }
262
263 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
266 cpuXC->setFloatReg(reg_idx, val);
266 thread->setFloatReg(reg_idx, val);
267 result.fp = val;
268 }
269
270 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
271 int width)
272 {
273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
267 result.fp = val;
268 }
269
270 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
271 int width)
272 {
273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
274 cpuXC->setFloatRegBits(reg_idx, val, width);
274 thread->setFloatRegBits(reg_idx, val, width);
275 result.integer = val;
276 }
277
278 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
279 {
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
275 result.integer = val;
276 }
277
278 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
279 {
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
281 cpuXC->setFloatRegBits(reg_idx, val);
281 thread->setFloatRegBits(reg_idx, val);
282 result.integer = val;
283 }
284
282 result.integer = val;
283 }
284
285 uint64_t readPC() { return cpuXC->readPC(); }
285 uint64_t readPC() { return thread->readPC(); }
286
286
287 uint64_t readNextPC() { return cpuXC->readNextPC(); }
287 uint64_t readNextPC() { return thread->readNextPC(); }
288
289 void setNextPC(uint64_t val) {
288
289 void setNextPC(uint64_t val) {
290 cpuXC->setNextPC(val);
290 thread->setNextPC(val);
291 }
292
293 MiscReg readMiscReg(int misc_reg)
294 {
291 }
292
293 MiscReg readMiscReg(int misc_reg)
294 {
295 return cpuXC->readMiscReg(misc_reg);
295 return thread->readMiscReg(misc_reg);
296 }
297
298 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
299 {
296 }
297
298 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
299 {
300 return cpuXC->readMiscRegWithEffect(misc_reg, fault);
300 return thread->readMiscRegWithEffect(misc_reg, fault);
301 }
302
303 Fault setMiscReg(int misc_reg, const MiscReg &val)
304 {
305 result.integer = val;
306 miscRegIdxs.push(misc_reg);
301 }
302
303 Fault setMiscReg(int misc_reg, const MiscReg &val)
304 {
305 result.integer = val;
306 miscRegIdxs.push(misc_reg);
307 return cpuXC->setMiscReg(misc_reg, val);
307 return thread->setMiscReg(misc_reg, val);
308 }
309
310 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
311 {
312 miscRegIdxs.push(misc_reg);
308 }
309
310 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
311 {
312 miscRegIdxs.push(misc_reg);
313 return cpuXC->setMiscRegWithEffect(misc_reg, val);
313 return thread->setMiscRegWithEffect(misc_reg, val);
314 }
315
316 void recordPCChange(uint64_t val) { changedPC = true; }
317 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
318
319 bool translateInstReq(Request *req);
320 void translateDataWriteReq(Request *req);
321 void translateDataReadReq(Request *req);
322
323#if FULL_SYSTEM
314 }
315
316 void recordPCChange(uint64_t val) { changedPC = true; }
317 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
318
319 bool translateInstReq(Request *req);
320 void translateDataWriteReq(Request *req);
321 void translateDataReadReq(Request *req);
322
323#if FULL_SYSTEM
324 Fault hwrei() { return cpuXC->hwrei(); }
325 int readIntrFlag() { return cpuXC->readIntrFlag(); }
326 void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
327 bool inPalMode() { return cpuXC->inPalMode(); }
324 Fault hwrei() { return thread->hwrei(); }
325 int readIntrFlag() { return thread->readIntrFlag(); }
326 void setIntrFlag(int val) { thread->setIntrFlag(val); }
327 bool inPalMode() { return thread->inPalMode(); }
328 void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
328 void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
329 bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
329 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
330#else
331 // Assume that the normal CPU's call to syscall was successful.
332 // The checker's state would have already been updated by the syscall.
333 void syscall(uint64_t callnum) { }
334#endif
335
336 void handleError()
337 {
338 if (exitOnError)
339 panic("Checker found error!");
340 }
341 bool checkFlags(Request *req);
342
343 ThreadContext *tcBase() { return tc; }
330#else
331 // Assume that the normal CPU's call to syscall was successful.
332 // The checker's state would have already been updated by the syscall.
333 void syscall(uint64_t callnum) { }
334#endif
335
336 void handleError()
337 {
338 if (exitOnError)
339 panic("Checker found error!");
340 }
341 bool checkFlags(Request *req);
342
343 ThreadContext *tcBase() { return tc; }
344 CPUExecContext *cpuXCBase() { return cpuXC; }
344 SimpleThread *threadBase() { return thread; }
345
346 Result unverifiedResult;
347 Request *unverifiedReq;
348 uint8_t *unverifiedMemData;
349
350 bool changedPC;
351 bool willChangePC;
352 uint64_t newPC;

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346 Result unverifiedResult;
347 Request *unverifiedReq;
348 uint8_t *unverifiedMemData;
349
350 bool changedPC;
351 bool willChangePC;
352 uint64_t newPC;

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