cpu.hh (2679:737e9f158843) cpu.hh (2680:246e7104f744)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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55
56#else
57
58class Process;
59
60#endif // FULL_SYSTEM
61template <class>
62class BaseDynInst;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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55
56#else
57
58class Process;
59
60#endif // FULL_SYSTEM
61template <class>
62class BaseDynInst;
63class ExecContext;
63class ThreadContext;
64class MemInterface;
65class Checkpoint;
66class Request;
67class Sampler;
68
69/**
70 * CheckerCPU class. Dynamically verifies instructions as they are
71 * completed by making sure that the instruction and its results match
72 * the independent execution of the benchmark inside the checker. The
73 * checker verifies instructions in order, regardless of the order in
74 * which instructions complete. There are certain results that can
75 * not be verified, specifically the result of a store conditional or
76 * the values of uncached accesses. In these cases, and with
77 * instructions marked as "IsUnverifiable", the checker assumes that
78 * the value from the main CPU's execution is correct and simply
64class MemInterface;
65class Checkpoint;
66class Request;
67class Sampler;
68
69/**
70 * CheckerCPU class. Dynamically verifies instructions as they are
71 * completed by making sure that the instruction and its results match
72 * the independent execution of the benchmark inside the checker. The
73 * checker verifies instructions in order, regardless of the order in
74 * which instructions complete. There are certain results that can
75 * not be verified, specifically the result of a store conditional or
76 * the values of uncached accesses. In these cases, and with
77 * instructions marked as "IsUnverifiable", the checker assumes that
78 * the value from the main CPU's execution is correct and simply
79 * copies that value. It provides a CheckerExecContext (see
79 * copies that value. It provides a CheckerThreadContext (see
80 * checker/exec_context.hh) that provides hooks for updating the
80 * checker/exec_context.hh) that provides hooks for updating the
81 * Checker's state through any ExecContext accesses. This allows the
81 * Checker's state through any ThreadContext accesses. This allows the
82 * checker to be able to correctly verify instructions, even with
82 * checker to be able to correctly verify instructions, even with
83 * external accesses to the ExecContext that change state.
83 * external accesses to the ThreadContext that change state.
84 */
85class CheckerCPU : public BaseCPU
86{
87 protected:
88 typedef TheISA::MachInst MachInst;
89 typedef TheISA::FloatReg FloatReg;
90 typedef TheISA::FloatRegBits FloatRegBits;
91 typedef TheISA::MiscReg MiscReg;

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127 void setDcachePort(Port *dcache_port);
128
129 Port *dcachePort;
130
131 public:
132 // execution context
133 CPUExecContext *cpuXC;
134
84 */
85class CheckerCPU : public BaseCPU
86{
87 protected:
88 typedef TheISA::MachInst MachInst;
89 typedef TheISA::FloatReg FloatReg;
90 typedef TheISA::FloatRegBits FloatRegBits;
91 typedef TheISA::MiscReg MiscReg;

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127 void setDcachePort(Port *dcache_port);
128
129 Port *dcachePort;
130
131 public:
132 // execution context
133 CPUExecContext *cpuXC;
134
135 ExecContext *xcProxy;
135 ThreadContext *tc;
136
137 AlphaITB *itb;
138 AlphaDTB *dtb;
139
140#if FULL_SYSTEM
141 Addr dbg_vtophys(Addr addr);
142#endif
143

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335
336 void handleError()
337 {
338 if (exitOnError)
339 panic("Checker found error!");
340 }
341 bool checkFlags(Request *req);
342
136
137 AlphaITB *itb;
138 AlphaDTB *dtb;
139
140#if FULL_SYSTEM
141 Addr dbg_vtophys(Addr addr);
142#endif
143

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335
336 void handleError()
337 {
338 if (exitOnError)
339 panic("Checker found error!");
340 }
341 bool checkFlags(Request *req);
342
343 ExecContext *xcBase() { return xcProxy; }
343 ThreadContext *tcBase() { return tc; }
344 CPUExecContext *cpuXCBase() { return cpuXC; }
345
346 Result unverifiedResult;
347 Request *unverifiedReq;
348 uint8_t *unverifiedMemData;
349
350 bool changedPC;
351 bool willChangePC;

--- 36 unchanged lines hidden --- 		344 CPUExecContext *cpuXCBase() { return cpuXC; }
345
346 Result unverifiedResult;
347 Request *unverifiedReq;
348 uint8_t *unverifiedMemData;
349
350 bool changedPC;
351 bool willChangePC;

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