cpu.hh (2674:6d4afef73a20) cpu.hh (2679:737e9f158843)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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103#endif
104 bool exitOnError;
105 };
106
107 public:
108 CheckerCPU(Params *p);
109 virtual ~CheckerCPU();
110
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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103#endif
104 bool exitOnError;
105 };
106
107 public:
108 CheckerCPU(Params *p);
109 virtual ~CheckerCPU();
110
111 Process *process;
112
111 void setMemory(MemObject *mem);
112
113 MemObject *memPtr;
114
115#if FULL_SYSTEM
116 void setSystem(System *system);
117
118 System *systemPtr;
119#endif
113 void setMemory(MemObject *mem);
114
115 MemObject *memPtr;
116
117#if FULL_SYSTEM
118 void setSystem(System *system);
119
120 System *systemPtr;
121#endif
122
123 void setIcachePort(Port *icache_port);
124
125 Port *icachePort;
126
127 void setDcachePort(Port *dcache_port);
128
129 Port *dcachePort;
130
120 public:
121 // execution context
122 CPUExecContext *cpuXC;
123
124 ExecContext *xcProxy;
125
126 AlphaITB *itb;
127 AlphaDTB *dtb;

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136 double dbl;
137 };
138
139 Result result;
140
141 // current instruction
142 MachInst machInst;
143
131 public:
132 // execution context
133 CPUExecContext *cpuXC;
134
135 ExecContext *xcProxy;
136
137 AlphaITB *itb;
138 AlphaDTB *dtb;

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147 double dbl;
148 };
149
150 Result result;
151
152 // current instruction
153 MachInst machInst;
154
144 // Refcounted pointer to the one memory request.
145 Request *memReq;
155 // Pointer to the one memory request.
156 RequestPtr memReq;
146
147 StaticInstPtr curStaticInst;
148
149 // number of simulated instructions
150 Counter numInst;
151 Counter startNumInst;
152
153 std::queue<int> miscRegIdxs;

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329 }
330 bool checkFlags(Request *req);
331
332 ExecContext *xcBase() { return xcProxy; }
333 CPUExecContext *cpuXCBase() { return cpuXC; }
334
335 Result unverifiedResult;
336 Request *unverifiedReq;
157
158 StaticInstPtr curStaticInst;
159
160 // number of simulated instructions
161 Counter numInst;
162 Counter startNumInst;
163
164 std::queue<int> miscRegIdxs;

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340 }
341 bool checkFlags(Request *req);
342
343 ExecContext *xcBase() { return xcProxy; }
344 CPUExecContext *cpuXCBase() { return cpuXC; }
345
346 Result unverifiedResult;
347 Request *unverifiedReq;
348 uint8_t *unverifiedMemData;
337
338 bool changedPC;
339 bool willChangePC;
340 uint64_t newPC;
341 bool changedNextPC;
342 bool exitOnError;
343
344 InstSeqNum youngestSN;

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350 bool changedPC;
351 bool willChangePC;
352 uint64_t newPC;
353 bool changedNextPC;
354 bool exitOnError;
355
356 InstSeqNum youngestSN;

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