cpu.hh (13954:2f400a5f2627) cpu.hh (14198:9c2f67392409)
1/*
2 * Copyright (c) 2011, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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100 virtual ~CheckerCPU();
101
102 void setSystem(System *system);
103
104 void setIcachePort(MasterPort *icache_port);
105
106 void setDcachePort(MasterPort *dcache_port);
107
1/*
2 * Copyright (c) 2011, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 91 unchanged lines hidden (view full) ---

100 virtual ~CheckerCPU();
101
102 void setSystem(System *system);
103
104 void setIcachePort(MasterPort *icache_port);
105
106 void setDcachePort(MasterPort *dcache_port);
107
108 MasterPort &getDataPort() override
108 Port &
109 getDataPort() override
109 {
110 // the checker does not have ports on its own so return the
111 // data port of the actual CPU core
112 assert(dcachePort);
113 return *dcachePort;
114 }
115
110 {
111 // the checker does not have ports on its own so return the
112 // data port of the actual CPU core
113 assert(dcachePort);
114 return *dcachePort;
115 }
116
116 MasterPort &getInstPort() override
117 Port &
118 getInstPort() override
117 {
118 // the checker does not have ports on its own so return the
119 // data port of the actual CPU core
120 assert(icachePort);
121 return *icachePort;
122 }
123
124 protected:

--- 542 unchanged lines hidden --- 		119 {
120 // the checker does not have ports on its own so return the
121 // data port of the actual CPU core
122 assert(icachePort);
123 return *icachePort;
124 }
125
126 protected:

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