cpu.hh (13652:45d94ac03a27) cpu.hh (13900:d4bcfecd871e)
1/*
2 * Copyright (c) 2011, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 469 unchanged lines hidden (view full) ---

478 void
479 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
480 {
481 const RegId& reg = si->destRegIdx(idx);
482 assert(reg.isMiscReg());
483 return this->setMiscReg(reg.index(), val);
484 }
485
1/*
2 * Copyright (c) 2011, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 469 unchanged lines hidden (view full) ---

478 void
479 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
480 {
481 const RegId& reg = si->destRegIdx(idx);
482 assert(reg.isMiscReg());
483 return this->setMiscReg(reg.index(), val);
484 }
485
486#if THE_ISA == MIPS_ISA
487 RegVal
488 readRegOtherThread(const RegId &misc_reg, ThreadID tid) override
489 {
490 panic("MIPS MT not defined for CheckerCPU.\n");
491 return 0;
492 }
493
494 void
495 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
496 {
497 panic("MIPS MT not defined for CheckerCPU.\n");
498 }
499#endif
500
501 /////////////////////////////////////////
502
503 void
504 recordPCChange(const TheISA::PCState &val)
505 {
506 changedPC = true;
507 newPCState = val;
508 }

--- 139 unchanged lines hidden --- 		486 /////////////////////////////////////////
487
488 void
489 recordPCChange(const TheISA::PCState &val)
490 {
491 changedPC = true;
492 newPCState = val;
493 }

--- 139 unchanged lines hidden ---