cpu.hh (13611:c8b7847b4171) cpu.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2011, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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315 VecPredRegContainer&
316 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
317 {
318 const RegId& reg = si->destRegIdx(idx);
319 assert(reg.isVecPredReg());
320 return thread->getWritableVecPredReg(reg);
321 }
322
1/*
2 * Copyright (c) 2011, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 306 unchanged lines hidden (view full) ---

315 VecPredRegContainer&
316 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
317 {
318 const RegId& reg = si->destRegIdx(idx);
319 assert(reg.isVecPredReg());
320 return thread->getWritableVecPredReg(reg);
321 }
322
323 CCReg
323 RegVal
324 readCCRegOperand(const StaticInst *si, int idx) override
325 {
326 const RegId& reg = si->srcRegIdx(idx);
327 assert(reg.isCCReg());
328 return thread->readCCReg(reg.index());
329 }
330
331 template<typename T>

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374 {
375 const RegId& reg = si->destRegIdx(idx);
376 assert(reg.isFloatReg());
377 thread->setFloatReg(reg.index(), val);
378 setScalarResult(val);
379 }
380
381 void
324 readCCRegOperand(const StaticInst *si, int idx) override
325 {
326 const RegId& reg = si->srcRegIdx(idx);
327 assert(reg.isCCReg());
328 return thread->readCCReg(reg.index());
329 }
330
331 template<typename T>

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374 {
375 const RegId& reg = si->destRegIdx(idx);
376 assert(reg.isFloatReg());
377 thread->setFloatReg(reg.index(), val);
378 setScalarResult(val);
379 }
380
381 void
382 setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
382 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
383 {
384 const RegId& reg = si->destRegIdx(idx);
385 assert(reg.isCCReg());
386 thread->setCCReg(reg.index(), val);
387 setScalarResult((uint64_t)val);
388 }
389
390 void

--- 250 unchanged lines hidden --- 		383 {
384 const RegId& reg = si->destRegIdx(idx);
385 assert(reg.isCCReg());
386 thread->setCCReg(reg.index(), val);
387 setScalarResult((uint64_t)val);
388 }
389
390 void

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