cpu.hh (12109:f29e9c5418aa) cpu.hh (12406:86bde4a026b5)
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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57#include "cpu/pc_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/static_inst.hh"
60#include "debug/Checker.hh"
61#include "mem/request.hh"
62#include "params/CheckerCPU.hh"
63#include "sim/eventq.hh"
64
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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57#include "cpu/pc_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/static_inst.hh"
60#include "debug/Checker.hh"
61#include "mem/request.hh"
62#include "params/CheckerCPU.hh"
63#include "sim/eventq.hh"
64
65// forward declarations
66namespace TheISA
67{
68 class TLB;
69}
70
65class BaseTLB;
71template <class>
72class BaseDynInst;
73class ThreadContext;
74class Request;
75
76/**
77 * CheckerCPU class. Dynamically verifies instructions as they are
78 * completed by making sure that the instruction and its results match

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135
136 System *systemPtr;
137
138 MasterPort *icachePort;
139 MasterPort *dcachePort;
140
141 ThreadContext *tc;
142
66template <class>
67class BaseDynInst;
68class ThreadContext;
69class Request;
70
71/**
72 * CheckerCPU class. Dynamically verifies instructions as they are
73 * completed by making sure that the instruction and its results match

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130
131 System *systemPtr;
132
133 MasterPort *icachePort;
134 MasterPort *dcachePort;
135
136 ThreadContext *tc;
137
143 TheISA::TLB *itb;
144 TheISA::TLB *dtb;
138 BaseTLB *itb;
139 BaseTLB *dtb;
145
146 Addr dbg_vtophys(Addr addr);
147
148 // ISAs like ARM can have multiple destination registers to check,
149 // keep them all in a std::queue
150 std::queue<InstResult> result;
151
152 // Pointer to the one memory request.

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161
162 std::queue<int> miscRegIdxs;
163
164 public:
165
166 // Primary thread being run.
167 SimpleThread *thread;
168
140
141 Addr dbg_vtophys(Addr addr);
142
143 // ISAs like ARM can have multiple destination registers to check,
144 // keep them all in a std::queue
145 std::queue<InstResult> result;
146
147 // Pointer to the one memory request.

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156
157 std::queue<int> miscRegIdxs;
158
159 public:
160
161 // Primary thread being run.
162 SimpleThread *thread;
163
169 TheISA::TLB* getITBPtr() { return itb; }
170 TheISA::TLB* getDTBPtr() { return dtb; }
164 BaseTLB* getITBPtr() { return itb; }
165 BaseTLB* getDTBPtr() { return dtb; }
171
172 virtual Counter totalInsts() const override
173 {
174 return 0;
175 }
176
177 virtual Counter totalOps() const override
178 {

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167 virtual Counter totalInsts() const override
168 {
169 return 0;
170 }
171
172 virtual Counter totalOps() const override
173 {

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