cpu.hh (12107:998b4c54ee51) cpu.hh (12109:f29e9c5418aa)
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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91 */
92class CheckerCPU : public BaseCPU, public ExecContext
93{
94 protected:
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
98 typedef TheISA::MiscReg MiscReg;
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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91 */
92class CheckerCPU : public BaseCPU, public ExecContext
93{
94 protected:
95 typedef TheISA::MachInst MachInst;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
98 typedef TheISA::MiscReg MiscReg;
99 using VecRegContainer = TheISA::VecRegContainer;
99
100 /** id attached to all issued requests */
101 MasterID masterId;
102 public:
103 void init() override;
104
105 typedef CheckerCPUParams Params;
106 CheckerCPU(Params *p);

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220 FloatRegBits readFloatRegOperandBits(const StaticInst *si,
221 int idx) override
222 {
223 const RegId& reg = si->srcRegIdx(idx);
224 assert(reg.isFloatReg());
225 return thread->readFloatRegBits(reg.index());
226 }
227
100
101 /** id attached to all issued requests */
102 MasterID masterId;
103 public:
104 void init() override;
105
106 typedef CheckerCPUParams Params;
107 CheckerCPU(Params *p);

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221 FloatRegBits readFloatRegOperandBits(const StaticInst *si,
222 int idx) override
223 {
224 const RegId& reg = si->srcRegIdx(idx);
225 assert(reg.isFloatReg());
226 return thread->readFloatRegBits(reg.index());
227 }
228
229 /**
230 * Read source vector register operand.
231 */
232 const VecRegContainer& readVecRegOperand(const StaticInst *si,
233 int idx) const override
234 {
235 const RegId& reg = si->srcRegIdx(idx);
236 assert(reg.isVecReg());
237 return thread->readVecReg(reg);
238 }
239
240 /**
241 * Read destination vector register operand for modification.
242 */
243 VecRegContainer& getWritableVecRegOperand(const StaticInst *si,
244 int idx) override
245 {
246 const RegId& reg = si->destRegIdx(idx);
247 assert(reg.isVecReg());
248 return thread->getWritableVecReg(reg);
249 }
250
251 /** Vector Register Lane Interfaces. */
252 /** @{ */
253 /** Reads source vector 8bit operand. */
254 virtual ConstVecLane8
255 readVec8BitLaneOperand(const StaticInst *si, int idx) const
256 override
257 {
258 const RegId& reg = si->destRegIdx(idx);
259 assert(reg.isVecReg());
260 return thread->readVec8BitLaneReg(reg);
261 }
262
263 /** Reads source vector 16bit operand. */
264 virtual ConstVecLane16
265 readVec16BitLaneOperand(const StaticInst *si, int idx) const
266 override
267 {
268 const RegId& reg = si->destRegIdx(idx);
269 assert(reg.isVecReg());
270 return thread->readVec16BitLaneReg(reg);
271 }
272
273 /** Reads source vector 32bit operand. */
274 virtual ConstVecLane32
275 readVec32BitLaneOperand(const StaticInst *si, int idx) const
276 override
277 {
278 const RegId& reg = si->destRegIdx(idx);
279 assert(reg.isVecReg());
280 return thread->readVec32BitLaneReg(reg);
281 }
282
283 /** Reads source vector 64bit operand. */
284 virtual ConstVecLane64
285 readVec64BitLaneOperand(const StaticInst *si, int idx) const
286 override
287 {
288 const RegId& reg = si->destRegIdx(idx);
289 assert(reg.isVecReg());
290 return thread->readVec64BitLaneReg(reg);
291 }
292
293 /** Write a lane of the destination vector operand. */
294 template <typename LD>
295 void
296 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
297 {
298 const RegId& reg = si->destRegIdx(idx);
299 assert(reg.isVecReg());
300 return thread->setVecLane(reg, val);
301 }
302 virtual void
303 setVecLaneOperand(const StaticInst *si, int idx,
304 const LaneData<LaneSize::Byte>& val) override
305 {
306 setVecLaneOperandT(si, idx, val);
307 }
308 virtual void
309 setVecLaneOperand(const StaticInst *si, int idx,
310 const LaneData<LaneSize::TwoByte>& val) override
311 {
312 setVecLaneOperandT(si, idx, val);
313 }
314 virtual void
315 setVecLaneOperand(const StaticInst *si, int idx,
316 const LaneData<LaneSize::FourByte>& val) override
317 {
318 setVecLaneOperandT(si, idx, val);
319 }
320 virtual void
321 setVecLaneOperand(const StaticInst *si, int idx,
322 const LaneData<LaneSize::EightByte>& val) override
323 {
324 setVecLaneOperandT(si, idx, val);
325 }
326 /** @} */
327
328 VecElem readVecElemOperand(const StaticInst *si, int idx) const override
329 {
330 const RegId& reg = si->srcRegIdx(idx);
331 return thread->readVecElem(reg);
332 }
333
228 CCReg readCCRegOperand(const StaticInst *si, int idx) override
229 {
230 const RegId& reg = si->srcRegIdx(idx);
231 assert(reg.isCCReg());
232 return thread->readCCReg(reg.index());
233 }
234
235 template<typename T>
236 void setScalarResult(T&& t)
237 {
238 result.push(InstResult(std::forward<T>(t),
239 InstResult::ResultType::Scalar));
240 }
241
334 CCReg readCCRegOperand(const StaticInst *si, int idx) override
335 {
336 const RegId& reg = si->srcRegIdx(idx);
337 assert(reg.isCCReg());
338 return thread->readCCReg(reg.index());
339 }
340
341 template<typename T>
342 void setScalarResult(T&& t)
343 {
344 result.push(InstResult(std::forward<T>(t),
345 InstResult::ResultType::Scalar));
346 }
347
348 template<typename T>
349 void setVecResult(T&& t)
350 {
351 result.push(InstResult(std::forward<T>(t),
352 InstResult::ResultType::VecReg));
353 }
354
355 template<typename T>
356 void setVecElemResult(T&& t)
357 {
358 result.push(InstResult(std::forward<T>(t),
359 InstResult::ResultType::VecElem));
360 }
361
242 void setIntRegOperand(const StaticInst *si, int idx,
243 IntReg val) override
244 {
245 const RegId& reg = si->destRegIdx(idx);
246 assert(reg.isIntReg());
247 thread->setIntReg(reg.index(), val);
248 setScalarResult(val);
249 }

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269 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
270 {
271 const RegId& reg = si->destRegIdx(idx);
272 assert(reg.isCCReg());
273 thread->setCCReg(reg.index(), val);
274 setScalarResult((uint64_t)val);
275 }
276
362 void setIntRegOperand(const StaticInst *si, int idx,
363 IntReg val) override
364 {
365 const RegId& reg = si->destRegIdx(idx);
366 assert(reg.isIntReg());
367 thread->setIntReg(reg.index(), val);
368 setScalarResult(val);
369 }

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389 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
390 {
391 const RegId& reg = si->destRegIdx(idx);
392 assert(reg.isCCReg());
393 thread->setCCReg(reg.index(), val);
394 setScalarResult((uint64_t)val);
395 }
396
397 void setVecRegOperand(const StaticInst *si, int idx,
398 const VecRegContainer& val) override
399 {
400 const RegId& reg = si->destRegIdx(idx);
401 assert(reg.isVecReg());
402 thread->setVecReg(reg, val);
403 setVecResult(val);
404 }
405
406 void setVecElemOperand(const StaticInst *si, int idx,
407 const VecElem val) override
408 {
409 const RegId& reg = si->destRegIdx(idx);
410 assert(reg.isVecElem());
411 thread->setVecElem(reg, val);
412 setVecElemResult(val);
413 }
414
277 bool readPredicate() override { return thread->readPredicate(); }
278 void setPredicate(bool val) override
279 {
280 thread->setPredicate(val);
281 }
282
283 TheISA::PCState pcState() const override { return thread->pcState(); }
284 void pcState(const TheISA::PCState &val) override

--- 199 unchanged lines hidden --- 		415 bool readPredicate() override { return thread->readPredicate(); }
416 void setPredicate(bool val) override
417 {
418 thread->setPredicate(val);
419 }
420
421 TheISA::PCState pcState() const override { return thread->pcState(); }
422 void pcState(const TheISA::PCState &val) override

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