cpu.hh (12104:edd63f9c6184) cpu.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 IntReg readIntRegOperand(const StaticInst *si, int idx) override
215 {
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 199 unchanged lines hidden (view full) ---

208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 IntReg readIntRegOperand(const StaticInst *si, int idx) override
215 {
216 RegId reg = si->srcRegIdx(idx);
217 assert(reg.regClass == IntRegClass);
218 return thread->readIntReg(reg.regIdx);
216 const RegId& reg = si->srcRegIdx(idx);
217 assert(reg.isIntReg());
218 return thread->readIntReg(reg.index());
219 }
220
221 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
222 {
219 }
220
221 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
222 {
223 RegId reg = si->srcRegIdx(idx);
224 assert(reg.regClass == FloatRegClass);
225 return thread->readFloatReg(reg.regIdx);
223 const RegId& reg = si->srcRegIdx(idx);
224 assert(reg.isFloatReg());
225 return thread->readFloatReg(reg.index());
226 }
227
228 FloatRegBits readFloatRegOperandBits(const StaticInst *si,
229 int idx) override
230 {
226 }
227
228 FloatRegBits readFloatRegOperandBits(const StaticInst *si,
229 int idx) override
230 {
231 RegId reg = si->srcRegIdx(idx);
232 assert(reg.regClass == FloatRegClass);
233 return thread->readFloatRegBits(reg.regIdx);
231 const RegId& reg = si->srcRegIdx(idx);
232 assert(reg.isFloatReg());
233 return thread->readFloatRegBits(reg.index());
234 }
235
236 CCReg readCCRegOperand(const StaticInst *si, int idx) override
237 {
234 }
235
236 CCReg readCCRegOperand(const StaticInst *si, int idx) override
237 {
238 RegId reg = si->srcRegIdx(idx);
239 assert(reg.regClass == CCRegClass);
240 return thread->readCCReg(reg.regIdx);
238 const RegId& reg = si->srcRegIdx(idx);
239 assert(reg.isCCReg());
240 return thread->readCCReg(reg.index());
241 }
242
243 template <class T>
244 void setResult(T t)
245 {
246 Result instRes;
247 instRes.set(t);
248 result.push(instRes);
249 }
250
251 void setIntRegOperand(const StaticInst *si, int idx,
252 IntReg val) override
253 {
241 }
242
243 template <class T>
244 void setResult(T t)
245 {
246 Result instRes;
247 instRes.set(t);
248 result.push(instRes);
249 }
250
251 void setIntRegOperand(const StaticInst *si, int idx,
252 IntReg val) override
253 {
254 RegId reg = si->destRegIdx(idx);
255 assert(reg.regClass == IntRegClass);
256 thread->setIntReg(reg.regIdx, val);
254 const RegId& reg = si->destRegIdx(idx);
255 assert(reg.isIntReg());
256 thread->setIntReg(reg.index(), val);
257 setResult<uint64_t>(val);
258 }
259
260 void setFloatRegOperand(const StaticInst *si, int idx,
261 FloatReg val) override
262 {
257 setResult<uint64_t>(val);
258 }
259
260 void setFloatRegOperand(const StaticInst *si, int idx,
261 FloatReg val) override
262 {
263 RegId reg = si->destRegIdx(idx);
264 assert(reg.regClass == FloatRegClass);
265 thread->setFloatReg(reg.regIdx, val);
263 const RegId& reg = si->destRegIdx(idx);
264 assert(reg.isFloatReg());
265 thread->setFloatReg(reg.index(), val);
266 setResult<double>(val);
267 }
268
269 void setFloatRegOperandBits(const StaticInst *si, int idx,
270 FloatRegBits val) override
271 {
266 setResult<double>(val);
267 }
268
269 void setFloatRegOperandBits(const StaticInst *si, int idx,
270 FloatRegBits val) override
271 {
272 RegId reg = si->destRegIdx(idx);
273 assert(reg.regClass == FloatRegClass);
274 thread->setFloatRegBits(reg.regIdx, val);
272 const RegId& reg = si->destRegIdx(idx);
273 assert(reg.isFloatReg());
274 thread->setFloatRegBits(reg.index(), val);
275 setResult<uint64_t>(val);
276 }
277
278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
279 {
275 setResult<uint64_t>(val);
276 }
277
278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
279 {
280 RegId reg = si->destRegIdx(idx);
281 assert(reg.regClass == CCRegClass);
282 thread->setCCReg(reg.regIdx, val);
280 const RegId& reg = si->destRegIdx(idx);
281 assert(reg.isCCReg());
282 thread->setCCReg(reg.index(), val);
283 setResult<uint64_t>(val);
284 }
285
286 bool readPredicate() override { return thread->readPredicate(); }
287 void setPredicate(bool val) override
288 {
289 thread->setPredicate(val);
290 }

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322 {
323 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
324 miscRegIdxs.push(misc_reg);
325 return thread->setMiscReg(misc_reg, val);
326 }
327
328 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
329 {
283 setResult<uint64_t>(val);
284 }
285
286 bool readPredicate() override { return thread->readPredicate(); }
287 void setPredicate(bool val) override
288 {
289 thread->setPredicate(val);
290 }

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322 {
323 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
324 miscRegIdxs.push(misc_reg);
325 return thread->setMiscReg(misc_reg, val);
326 }
327
328 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
329 {
330 RegId reg = si->srcRegIdx(idx);
331 assert(reg.regClass == MiscRegClass);
332 return thread->readMiscReg(reg.regIdx);
330 const RegId& reg = si->srcRegIdx(idx);
331 assert(reg.isMiscReg());
332 return thread->readMiscReg(reg.index());
333 }
334
335 void setMiscRegOperand(const StaticInst *si, int idx,
336 const MiscReg &val) override
337 {
333 }
334
335 void setMiscRegOperand(const StaticInst *si, int idx,
336 const MiscReg &val) override
337 {
338 RegId reg = si->destRegIdx(idx);
339 assert(reg.regClass == MiscRegClass);
340 return this->setMiscReg(reg.regIdx, val);
338 const RegId& reg = si->destRegIdx(idx);
339 assert(reg.isMiscReg());
340 return this->setMiscReg(reg.index(), val);
341 }
342
343#if THE_ISA == MIPS_ISA
341 }
342
343#if THE_ISA == MIPS_ISA
344 MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override
344 MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
345 {
346 panic("MIPS MT not defined for CheckerCPU.\n");
347 return 0;
348 }
349
345 {
346 panic("MIPS MT not defined for CheckerCPU.\n");
347 return 0;
348 }
349
350 void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override
350 void setRegOtherThread(const RegId& misc_reg, MiscReg val,
351 ThreadID tid) override
351 {
352 panic("MIPS MT not defined for CheckerCPU.\n");
353 }
354#endif
355
356 /////////////////////////////////////////
357
358 void recordPCChange(const TheISA::PCState &val)

--- 132 unchanged lines hidden --- 		352 {
353 panic("MIPS MT not defined for CheckerCPU.\n");
354 }
355#endif
356
357 /////////////////////////////////////////
358
359 void recordPCChange(const TheISA::PCState &val)

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