cpu.hh (11877:5ea85692a53e) cpu.hh (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 IntReg readIntRegOperand(const StaticInst *si, int idx) override
215 {
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 199 unchanged lines hidden (view full) ---

208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 IntReg readIntRegOperand(const StaticInst *si, int idx) override
215 {
216 return thread->readIntReg(si->srcRegIdx(idx));
216 RegId reg = si->srcRegIdx(idx);
217 assert(reg.regClass == IntRegClass);
218 return thread->readIntReg(reg.regIdx);
217 }
218
219 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
220 {
219 }
220
221 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
222 {
221 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
222 return thread->readFloatReg(reg_idx);
223 RegId reg = si->srcRegIdx(idx);
224 assert(reg.regClass == FloatRegClass);
225 return thread->readFloatReg(reg.regIdx);
223 }
224
225 FloatRegBits readFloatRegOperandBits(const StaticInst *si,
226 int idx) override
227 {
226 }
227
228 FloatRegBits readFloatRegOperandBits(const StaticInst *si,
229 int idx) override
230 {
228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
229 return thread->readFloatRegBits(reg_idx);
231 RegId reg = si->srcRegIdx(idx);
232 assert(reg.regClass == FloatRegClass);
233 return thread->readFloatRegBits(reg.regIdx);
230 }
231
232 CCReg readCCRegOperand(const StaticInst *si, int idx) override
233 {
234 }
235
236 CCReg readCCRegOperand(const StaticInst *si, int idx) override
237 {
234 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
235 return thread->readCCReg(reg_idx);
238 RegId reg = si->srcRegIdx(idx);
239 assert(reg.regClass == CCRegClass);
240 return thread->readCCReg(reg.regIdx);
236 }
237
238 template <class T>
239 void setResult(T t)
240 {
241 Result instRes;
242 instRes.set(t);
243 result.push(instRes);
244 }
245
246 void setIntRegOperand(const StaticInst *si, int idx,
247 IntReg val) override
248 {
241 }
242
243 template <class T>
244 void setResult(T t)
245 {
246 Result instRes;
247 instRes.set(t);
248 result.push(instRes);
249 }
250
251 void setIntRegOperand(const StaticInst *si, int idx,
252 IntReg val) override
253 {
249 thread->setIntReg(si->destRegIdx(idx), val);
254 RegId reg = si->destRegIdx(idx);
255 assert(reg.regClass == IntRegClass);
256 thread->setIntReg(reg.regIdx, val);
250 setResult<uint64_t>(val);
251 }
252
253 void setFloatRegOperand(const StaticInst *si, int idx,
254 FloatReg val) override
255 {
257 setResult<uint64_t>(val);
258 }
259
260 void setFloatRegOperand(const StaticInst *si, int idx,
261 FloatReg val) override
262 {
256 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
257 thread->setFloatReg(reg_idx, val);
263 RegId reg = si->destRegIdx(idx);
264 assert(reg.regClass == FloatRegClass);
265 thread->setFloatReg(reg.regIdx, val);
258 setResult<double>(val);
259 }
260
261 void setFloatRegOperandBits(const StaticInst *si, int idx,
262 FloatRegBits val) override
263 {
266 setResult<double>(val);
267 }
268
269 void setFloatRegOperandBits(const StaticInst *si, int idx,
270 FloatRegBits val) override
271 {
264 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
265 thread->setFloatRegBits(reg_idx, val);
272 RegId reg = si->destRegIdx(idx);
273 assert(reg.regClass == FloatRegClass);
274 thread->setFloatRegBits(reg.regIdx, val);
266 setResult<uint64_t>(val);
267 }
268
269 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
270 {
275 setResult<uint64_t>(val);
276 }
277
278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
279 {
271 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
272 thread->setCCReg(reg_idx, val);
280 RegId reg = si->destRegIdx(idx);
281 assert(reg.regClass == CCRegClass);
282 thread->setCCReg(reg.regIdx, val);
273 setResult<uint64_t>(val);
274 }
275
276 bool readPredicate() override { return thread->readPredicate(); }
277 void setPredicate(bool val) override
278 {
279 thread->setPredicate(val);
280 }

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312 {
313 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
314 miscRegIdxs.push(misc_reg);
315 return thread->setMiscReg(misc_reg, val);
316 }
317
318 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
319 {
283 setResult<uint64_t>(val);
284 }
285
286 bool readPredicate() override { return thread->readPredicate(); }
287 void setPredicate(bool val) override
288 {
289 thread->setPredicate(val);
290 }

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322 {
323 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
324 miscRegIdxs.push(misc_reg);
325 return thread->setMiscReg(misc_reg, val);
326 }
327
328 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
329 {
320 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
321 return thread->readMiscReg(reg_idx);
330 RegId reg = si->srcRegIdx(idx);
331 assert(reg.regClass == MiscRegClass);
332 return thread->readMiscReg(reg.regIdx);
322 }
323
324 void setMiscRegOperand(const StaticInst *si, int idx,
325 const MiscReg &val) override
326 {
333 }
334
335 void setMiscRegOperand(const StaticInst *si, int idx,
336 const MiscReg &val) override
337 {
327 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
328 return this->setMiscReg(reg_idx, val);
338 RegId reg = si->destRegIdx(idx);
339 assert(reg.regClass == MiscRegClass);
340 return this->setMiscReg(reg.regIdx, val);
329 }
330
331#if THE_ISA == MIPS_ISA
341 }
342
343#if THE_ISA == MIPS_ISA
332 MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override
344 MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override
333 {
334 panic("MIPS MT not defined for CheckerCPU.\n");
335 return 0;
336 }
337
345 {
346 panic("MIPS MT not defined for CheckerCPU.\n");
347 return 0;
348 }
349
338 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override
350 void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override
339 {
340 panic("MIPS MT not defined for CheckerCPU.\n");
341 }
342#endif
343
344 /////////////////////////////////////////
345
346 void recordPCChange(const TheISA::PCState &val)

--- 132 unchanged lines hidden --- 		351 {
352 panic("MIPS MT not defined for CheckerCPU.\n");
353 }
354#endif
355
356 /////////////////////////////////////////
357
358 void recordPCChange(const TheISA::PCState &val)

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