cpu.hh (11151:ca4ea9b5c052) cpu.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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184 {
185 return 0;
186 }
187
188 // number of simulated loads
189 Counter numLoad;
190 Counter startNumLoad;
191
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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184 {
185 return 0;
186 }
187
188 // number of simulated loads
189 Counter numLoad;
190 Counter startNumLoad;
191
192 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
193 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
192 void serialize(CheckpointOut &cp) const override;
193 void unserialize(CheckpointIn &cp) override;
194
195 // These functions are only used in CPU models that split
196 // effective address computation from the actual memory access.
197 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
198 Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
199
200 // The register accessor methods provide the index of the
201 // instruction's operand (e.g., 0 or 1), not the architectural

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375 }
376
377 void setStCondFailures(unsigned int sc_failures)
378 {}
379 /////////////////////////////////////////////////////
380
381 Fault hwrei() { return thread->hwrei(); }
382 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
194
195 // These functions are only used in CPU models that split
196 // effective address computation from the actual memory access.
197 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
198 Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
199
200 // The register accessor methods provide the index of the
201 // instruction's operand (e.g., 0 or 1), not the architectural

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375 }
376
377 void setStCondFailures(unsigned int sc_failures)
378 {}
379 /////////////////////////////////////////////////////
380
381 Fault hwrei() { return thread->hwrei(); }
382 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
383 void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { }
383 void wakeup(ThreadID tid) override { }
384 // Assume that the normal CPU's call to syscall was successful.
385 // The checker's state would have already been updated by the syscall.
386 void syscall(int64_t callnum) { }
387
388 void handleError()
389 {
390 if (exitOnError)
391 dumpAndExit();

--- 77 unchanged lines hidden --- 		384 // Assume that the normal CPU's call to syscall was successful.
385 // The checker's state would have already been updated by the syscall.
386 void syscall(int64_t callnum) { }
387
388 void handleError()
389 {
390 if (exitOnError)
391 dumpAndExit();

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