cpu.hh (10034:f2ce7114b137) cpu.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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47#include <list>
48#include <map>
49#include <queue>
50
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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47#include <list>
48#include <map>
49#include <queue>
50
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exec_context.hh"
55#include "cpu/pc_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/static_inst.hh"
58#include "debug/Checker.hh"
59#include "params/CheckerCPU.hh"
60#include "sim/eventq.hh"
61
62// forward declarations

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81 * instructions marked as "IsUnverifiable", the checker assumes that
82 * the value from the main CPU's execution is correct and simply
83 * copies that value. It provides a CheckerThreadContext (see
84 * checker/thread_context.hh) that provides hooks for updating the
85 * Checker's state through any ThreadContext accesses. This allows the
86 * checker to be able to correctly verify instructions, even with
87 * external accesses to the ThreadContext that change state.
88 */
56#include "cpu/pc_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/static_inst.hh"
59#include "debug/Checker.hh"
60#include "params/CheckerCPU.hh"
61#include "sim/eventq.hh"
62
63// forward declarations

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82 * instructions marked as "IsUnverifiable", the checker assumes that
83 * the value from the main CPU's execution is correct and simply
84 * copies that value. It provides a CheckerThreadContext (see
85 * checker/thread_context.hh) that provides hooks for updating the
86 * Checker's state through any ThreadContext accesses. This allows the
87 * checker to be able to correctly verify instructions, even with
88 * external accesses to the ThreadContext that change state.
89 */
89class CheckerCPU : public BaseCPU
90class CheckerCPU : public BaseCPU, public ExecContext
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
96
97 /** id attached to all issued requests */

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189 Counter startNumLoad;
190
191 virtual void serialize(std::ostream &os);
192 virtual void unserialize(Checkpoint *cp, const std::string &section);
193
194 // These functions are only used in CPU models that split
195 // effective address computation from the actual memory access.
196 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
91{
92 protected:
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96 typedef TheISA::MiscReg MiscReg;
97
98 /** id attached to all issued requests */

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190 Counter startNumLoad;
191
192 virtual void serialize(std::ostream &os);
193 virtual void unserialize(Checkpoint *cp, const std::string &section);
194
195 // These functions are only used in CPU models that split
196 // effective address computation from the actual memory access.
197 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
197 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
198 Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
198
199 // The register accessor methods provide the index of the
200 // instruction's operand (e.g., 0 or 1), not the architectural
201 // register index, to simplify the implementation of register
202 // renaming. We find the architectural register index by indexing
203 // into the instruction's own operand index table. Note that a
204 // raw pointer to the StaticInst is provided instead of a
205 // ref-counted StaticInstPtr to redice overhead. This is fine as
206 // long as these methods don't copy the pointer into any long-term
207 // storage (which is pretty hard to imagine they would have reason
208 // to do).
209
199
200 // The register accessor methods provide the index of the
201 // instruction's operand (e.g., 0 or 1), not the architectural
202 // register index, to simplify the implementation of register
203 // renaming. We find the architectural register index by indexing
204 // into the instruction's own operand index table. Note that a
205 // raw pointer to the StaticInst is provided instead of a
206 // ref-counted StaticInstPtr to redice overhead. This is fine as
207 // long as these methods don't copy the pointer into any long-term
208 // storage (which is pretty hard to imagine they would have reason
209 // to do).
210
210 uint64_t readIntRegOperand(const StaticInst *si, int idx)
211 IntReg readIntRegOperand(const StaticInst *si, int idx)
211 {
212 return thread->readIntReg(si->srcRegIdx(idx));
213 }
214
215 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
216 {
217 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
218 return thread->readFloatReg(reg_idx);
219 }
220
221 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
222 {
223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
224 return thread->readFloatRegBits(reg_idx);
225 }
226
212 {
213 return thread->readIntReg(si->srcRegIdx(idx));
214 }
215
216 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
217 {
218 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
219 return thread->readFloatReg(reg_idx);
220 }
221
222 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
223 {
224 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
225 return thread->readFloatRegBits(reg_idx);
226 }
227
227 uint64_t readCCRegOperand(const StaticInst *si, int idx)
228 CCReg readCCRegOperand(const StaticInst *si, int idx)
228 {
229 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
230 return thread->readCCReg(reg_idx);
231 }
232
233 template <class T>
234 void setResult(T t)
235 {
236 Result instRes;
237 instRes.set(t);
238 result.push(instRes);
239 }
240
229 {
230 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
231 return thread->readCCReg(reg_idx);
232 }
233
234 template <class T>
235 void setResult(T t)
236 {
237 Result instRes;
238 instRes.set(t);
239 result.push(instRes);
240 }
241
241 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
242 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
242 {
243 thread->setIntReg(si->destRegIdx(idx), val);
244 setResult<uint64_t>(val);
245 }
246
247 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
248 {
249 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;

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254 void setFloatRegOperandBits(const StaticInst *si, int idx,
255 FloatRegBits val)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
258 thread->setFloatRegBits(reg_idx, val);
259 setResult<uint64_t>(val);
260 }
261
243 {
244 thread->setIntReg(si->destRegIdx(idx), val);
245 setResult<uint64_t>(val);
246 }
247
248 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
249 {
250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;

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255 void setFloatRegOperandBits(const StaticInst *si, int idx,
256 FloatRegBits val)
257 {
258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
259 thread->setFloatRegBits(reg_idx, val);
260 setResult<uint64_t>(val);
261 }
262
262 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
263 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
263 {
264 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
265 thread->setCCReg(reg_idx, val);
266 setResult<uint64_t>(val);
267 }
268
269 bool readPredicate() { return thread->readPredicate(); }
270 void setPredicate(bool val)
271 {
272 thread->setPredicate(val);
273 }
274
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
266 thread->setCCReg(reg_idx, val);
267 setResult<uint64_t>(val);
268 }
269
270 bool readPredicate() { return thread->readPredicate(); }
271 void setPredicate(bool val)
272 {
273 thread->setPredicate(val);
274 }
275
275 TheISA::PCState pcState() { return thread->pcState(); }
276 TheISA::PCState pcState() const { return thread->pcState(); }
276 void pcState(const TheISA::PCState &val)
277 {
278 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
279 val, thread->pcState());
280 thread->pcState(val);
281 }
282 Addr instAddr() { return thread->instAddr(); }
283 Addr nextInstAddr() { return thread->nextInstAddr(); }

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317 void setMiscRegOperand(
318 const StaticInst *si, int idx, const MiscReg &val)
319 {
320 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
321 return this->setMiscReg(reg_idx, val);
322 }
323
324#if THE_ISA == MIPS_ISA
277 void pcState(const TheISA::PCState &val)
278 {
279 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
280 val, thread->pcState());
281 thread->pcState(val);
282 }
283 Addr instAddr() { return thread->instAddr(); }
284 Addr nextInstAddr() { return thread->nextInstAddr(); }

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318 void setMiscRegOperand(
319 const StaticInst *si, int idx, const MiscReg &val)
320 {
321 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
322 return this->setMiscReg(reg_idx, val);
323 }
324
325#if THE_ISA == MIPS_ISA
325 uint64_t readRegOtherThread(int misc_reg)
326 MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
326 {
327 panic("MIPS MT not defined for CheckerCPU.\n");
328 return 0;
329 }
330
327 {
328 panic("MIPS MT not defined for CheckerCPU.\n");
329 return 0;
330 }
331
331 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
332 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
332 {
333 panic("MIPS MT not defined for CheckerCPU.\n");
334 }
335#endif
336
337 /////////////////////////////////////////
338
339 void recordPCChange(const TheISA::PCState &val)

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357 {
358 this->dtb->demapPage(vaddr, asn);
359 }
360
361 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
362 Fault writeMem(uint8_t *data, unsigned size,
363 Addr addr, unsigned flags, uint64_t *res);
364
333 {
334 panic("MIPS MT not defined for CheckerCPU.\n");
335 }
336#endif
337
338 /////////////////////////////////////////
339
340 void recordPCChange(const TheISA::PCState &val)

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358 {
359 this->dtb->demapPage(vaddr, asn);
360 }
361
362 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
363 Fault writeMem(uint8_t *data, unsigned size,
364 Addr addr, unsigned flags, uint64_t *res);
365
365 void setStCondFailures(unsigned sc_failures)
366 unsigned int readStCondFailures() const {
367 return thread->readStCondFailures();
368 }
369
370 void setStCondFailures(unsigned int sc_failures)
366 {}
367 /////////////////////////////////////////////////////
368
369 Fault hwrei() { return thread->hwrei(); }
370 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
371 void wakeup() { }
372 // Assume that the normal CPU's call to syscall was successful.
373 // The checker's state would have already been updated by the syscall.
371 {}
372 /////////////////////////////////////////////////////
373
374 Fault hwrei() { return thread->hwrei(); }
375 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
376 void wakeup() { }
377 // Assume that the normal CPU's call to syscall was successful.
378 // The checker's state would have already been updated by the syscall.
374 void syscall(uint64_t callnum) { }
379 void syscall(int64_t callnum) { }
375
376 void handleError()
377 {
378 if (exitOnError)
379 dumpAndExit();
380 }
381
382 bool checkFlags(Request *unverified_req, Addr vAddr,

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381 void handleError()
382 {
383 if (exitOnError)
384 dumpAndExit();
385 }
386
387 bool checkFlags(Request *unverified_req, Addr vAddr,

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