1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 84 unchanged lines hidden (view full) --- 93 typedef TheISA::FloatRegBits FloatRegBits; 94 typedef TheISA::MiscReg MiscReg; 95 96 /** id attached to all issued requests */ 97 MasterID masterId; 98 public: 99 virtual void init(); 100 |
101 typedef CheckerCPUParams Params; |
102 CheckerCPU(Params *p); 103 virtual ~CheckerCPU(); 104 |
105 void setSystem(System *system); 106 |
107 void setIcachePort(CpuPort *icache_port); 108 |
109 void setDcachePort(CpuPort *dcache_port); 110 |
111 CpuPort &getDataPort() 112 { |
113 // the checker does not have ports on its own so return the 114 // data port of the actual CPU core 115 assert(dcachePort); |
116 return *dcachePort; 117 } 118 119 CpuPort &getInstPort() 120 { |
121 // the checker does not have ports on its own so return the 122 // data port of the actual CPU core 123 assert(icachePort); |
124 return *icachePort; 125 } 126 |
127 protected: |
128 |
129 std::vector<Process*> workload; 130 131 System *systemPtr; 132 133 CpuPort *icachePort; 134 CpuPort *dcachePort; 135 |
136 ThreadContext *tc; 137 138 TheISA::TLB *itb; 139 TheISA::TLB *dtb; 140 141 Addr dbg_vtophys(Addr addr); 142 143 union Result { --- 16 unchanged lines hidden (view full) --- 160 StaticInstPtr curMacroStaticInst; 161 162 // number of simulated instructions 163 Counter numInst; 164 Counter startNumInst; 165 166 std::queue<int> miscRegIdxs; 167 |
168 public: 169 170 // Primary thread being run. 171 SimpleThread *thread; 172 |
173 TheISA::TLB* getITBPtr() { return itb; } 174 TheISA::TLB* getDTBPtr() { return dtb; } 175 176 virtual Counter totalInsts() const 177 { 178 return 0; 179 } 180 --- 261 unchanged lines hidden --- |