1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 98 unchanged lines hidden (view full) --- 107 virtual ~CheckerCPU(); 108 109 std::vector<Process*> workload; 110 111 void setSystem(System *system); 112 113 System *systemPtr; 114 |
115 void setIcachePort(CpuPort *icache_port); |
116 |
117 CpuPort *icachePort; |
118 |
119 void setDcachePort(CpuPort *dcache_port); |
120 |
121 CpuPort *dcachePort; |
122 |
123 CpuPort &getDataPort() 124 { 125 panic("Not supported on checker!"); 126 return *dcachePort; 127 } 128 129 CpuPort &getInstPort() 130 { 131 panic("Not supported on checker!"); 132 return *icachePort; 133 } 134 |
135 virtual Port *getPort(const std::string &name, int idx) 136 { 137 panic("Not supported on checker!"); 138 return NULL; 139 } 140 141 public: 142 // Primary thread being run. --- 32 unchanged lines hidden (view full) --- 175 Counter numInst; 176 Counter startNumInst; 177 178 std::queue<int> miscRegIdxs; 179 180 TheISA::TLB* getITBPtr() { return itb; } 181 TheISA::TLB* getDTBPtr() { return dtb; } 182 |
183 virtual Counter totalInsts() const |
184 { 185 return 0; 186 } 187 |
188 virtual Counter totalOps() const 189 { 190 return 0; 191 } 192 |
193 // number of simulated loads 194 Counter numLoad; 195 Counter startNumLoad; 196 197 virtual void serialize(std::ostream &os); 198 virtual void unserialize(Checkpoint *cp, const std::string §ion); 199 200 // These functions are only used in CPU models that split --- 236 unchanged lines hidden --- |