1/* 2 * Copyright (c) 2011 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 80 unchanged lines hidden (view full) --- 89 */ 90class CheckerCPU : public BaseCPU, public ExecContext 91{ 92 protected: 93 typedef TheISA::MachInst MachInst; 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 typedef TheISA::MiscReg MiscReg; |
97 98 /** id attached to all issued requests */ 99 MasterID masterId; 100 public: 101 virtual void init(); 102 103 typedef CheckerCPUParams Params; 104 CheckerCPU(Params *p); --- 35 unchanged lines hidden (view full) --- 140 TheISA::TLB *itb; 141 TheISA::TLB *dtb; 142 143 Addr dbg_vtophys(Addr addr); 144 145 union Result { 146 uint64_t integer; 147 double dbl; |
148 void set(uint64_t i) { integer = i; } 149 void set(double d) { dbl = d; } |
150 void get(uint64_t& i) { i = integer; } 151 void get(double& d) { d = dbl; } |
152 }; 153 154 // ISAs like ARM can have multiple destination registers to check, 155 // keep them all in a std::queue 156 std::queue<Result> result; 157 158 // Pointer to the one memory request. 159 RequestPtr memReq; --- 66 unchanged lines hidden (view full) --- 226 } 227 228 CCReg readCCRegOperand(const StaticInst *si, int idx) 229 { 230 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 231 return thread->readCCReg(reg_idx); 232 } 233 |
234 template <class T> 235 void setResult(T t) 236 { 237 Result instRes; 238 instRes.set(t); 239 result.push(instRes); 240 } 241 --- 20 unchanged lines hidden (view full) --- 262 263 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 264 { 265 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 266 thread->setCCReg(reg_idx, val); 267 setResult<uint64_t>(val); 268 } 269 |
270 bool readPredicate() { return thread->readPredicate(); } 271 void setPredicate(bool val) 272 { 273 thread->setPredicate(val); 274 } 275 276 TheISA::PCState pcState() const { return thread->pcState(); } 277 void pcState(const TheISA::PCState &val) --- 158 unchanged lines hidden (view full) --- 436 void advancePC(const Fault &fault); 437 438 void verify(DynInstPtr &inst); 439 440 void validateInst(DynInstPtr &inst); 441 void validateExecution(DynInstPtr &inst); 442 void validateState(); 443 |
444 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); |
445 void handlePendingInt(); 446 447 private: 448 void handleError(DynInstPtr &inst) 449 { 450 if (exitOnError) { 451 dumpAndExit(inst); 452 } else if (updateOnError) { --- 16 unchanged lines hidden --- |