216,218c216,218
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == IntRegClass);
< return thread->readIntReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isIntReg());
> return thread->readIntReg(reg.index());
223,225c223,225
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< return thread->readFloatReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isFloatReg());
> return thread->readFloatReg(reg.index());
231,233c231,233
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< return thread->readFloatRegBits(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isFloatReg());
> return thread->readFloatRegBits(reg.index());
238,240c238,240
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == CCRegClass);
< return thread->readCCReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isCCReg());
> return thread->readCCReg(reg.index());
254,256c254,256
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == IntRegClass);
< thread->setIntReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isIntReg());
> thread->setIntReg(reg.index(), val);
263,265c263,265
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< thread->setFloatReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isFloatReg());
> thread->setFloatReg(reg.index(), val);
272,274c272,274
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< thread->setFloatRegBits(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isFloatReg());
> thread->setFloatRegBits(reg.index(), val);
280,282c280,282
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == CCRegClass);
< thread->setCCReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isCCReg());
> thread->setCCReg(reg.index(), val);
330,332c330,332
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == MiscRegClass);
< return thread->readMiscReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isMiscReg());
> return thread->readMiscReg(reg.index());
338,340c338,340
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == MiscRegClass);
< return this->setMiscReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isMiscReg());
> return this->setMiscReg(reg.index(), val);
344c344
< MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override
---
> MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
350c350,351
< void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override
---
> void setRegOtherThread(const RegId& misc_reg, MiscReg val,
> ThreadID tid) override