216c216,218
< return thread->readIntReg(si->srcRegIdx(idx));
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == IntRegClass);
> return thread->readIntReg(reg.regIdx);
221,222c223,225
< int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
< return thread->readFloatReg(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> return thread->readFloatReg(reg.regIdx);
228,229c231,233
< int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
< return thread->readFloatRegBits(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> return thread->readFloatRegBits(reg.regIdx);
234,235c238,240
< int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
< return thread->readCCReg(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == CCRegClass);
> return thread->readCCReg(reg.regIdx);
249c254,256
< thread->setIntReg(si->destRegIdx(idx), val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == IntRegClass);
> thread->setIntReg(reg.regIdx, val);
256,257c263,265
< int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
< thread->setFloatReg(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> thread->setFloatReg(reg.regIdx, val);
264,265c272,274
< int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
< thread->setFloatRegBits(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> thread->setFloatRegBits(reg.regIdx, val);
271,272c280,282
< int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
< thread->setCCReg(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == CCRegClass);
> thread->setCCReg(reg.regIdx, val);
320,321c330,332
< int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
< return thread->readMiscReg(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == MiscRegClass);
> return thread->readMiscReg(reg.regIdx);
327,328c338,340
< int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
< return this->setMiscReg(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == MiscRegClass);
> return this->setMiscReg(reg.regIdx, val);
332c344
< MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override
---
> MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override
338c350
< void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override
---
> void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override